Endri Bezati

Orcid: 0000-0003-3446-9838

According to our database1, Endri Bezati authored at least 50 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
ART: An Actor transition systems RunTime for enabling efficient partitioning of neural network graphs.
Proceedings of the 2023 Workshop on Compilers, Deployment, and Tooling for Edge AI, 2023

2022
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report).
CoRR, 2021

Generating hardware and software for RISC-V cores generated with Rocket Chip generator.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs.
J. Signal Process. Syst., 2020

Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Advanced Dataflow Programming using Actor Machines for High-Level Synthesis.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Dataflow-based Heterogeneous Code Generator for IoT Applications.
Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 2019

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism.
Proceedings of the Computational Science - ICCS 2019, 2019

An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs.
IEEE Trans. Multi Scale Comput. Syst., 2018

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Towards in the Field Fast Pathogens Detection Using FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design space exploration of dataflow-based Smith-Waterman FPGA implementations.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

High level synthesis of Smith-Waterman dataflow implementations.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms.
Proceedings of the 25th European Signal Processing Conference, 2017

Profiling of dynamic dataflow programs on MPSoC multi-core architectures.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Automated Design Flow for Multi-Functional Dataflow-Based Platforms.
J. Signal Process. Syst., 2016

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies.
J. Signal Process. Syst., 2016

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance estimation of program partitions on multi-core platforms.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

High-Precision Performance Estimation of Dynamic Dataflow Programs.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Programming Models and Methods for Heterogeneous Parallel Embedded Systems.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

A Partition Scheduler Model for Dynamic Dataflow Programs.
Proceedings of the International Conference on Computational Science 2016, 2016

Trace-based manycore partitioning of stream-processing applications.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

High-level system synthesis and optimization of dataflow programs for MPSoCs.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs.
Proceedings of the International Conference on Computational Science, 2015

2014
High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms.
J. Real Time Image Process., 2014

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

TURNUS: An open-source design space exploration framework for dynamic stream programs.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Dataflow machines.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Methods to explore design space for MPEG RMC codec specifications.
Signal Process. Image Commun., 2013

Partitioning and optimization of high level stream applications for multi clock domain architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Live demonstration: High level software and hardware synthesis of dataflow programs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High-level synthesis of dataflow programs for signal processing systems.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Design space exploration and implementation of RVC-CAL applications using the TURNUS framework.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs.
J. Electr. Comput. Eng., 2012

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

A unified hardware/software co-synthesis solution for signal processing systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010


  Loading...