Emre Salman

Mohammadamin Hajikhodaverdian

IEEE Trans. Consumer Electron., February, 2024

A New Dataflow Implementation to Improve Energy Efficiency of Monolithic 3D Systolic Arrays.

[BibT_eX]

[DOI]

CoRR, 2024

A Triboelectric Nanogenerator Interface Circuit for Applied Force Sensing.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Enhanced Detection of Thermal Covert Channel Attacks in Multicore Processors.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Energy-Efficient Dataflow Design for Monolithic 3D Systolic Arrays with Resistive RAM.

[BibT_eX]

[DOI]

Prachi Shukla

Vasilis F. Pavlidis

Ayse K. Coskun

Proceedings of the 15th IEEE International Green and Sustainable Computing Conference, 2024

2023

TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems.

[BibT_eX]

[DOI]

Sensors, February, 2023

SEAL-RF: Secure Adiabatic Logic for Wirelessly Powered IoT Devices.

[BibT_eX]

[DOI]

IEEE Internet Things J., January, 2023

Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators.

[BibT_eX]

[DOI]

Abrar Abdurrob

Jack Lombardi

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Information-Theoretic Perspective to Thermal Covert Channels.

[BibT_eX]

[DOI]

Krithika Yethiraj

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Precision and Performance-Aware Voltage Scaling in DNN Accelerators.

[BibT_eX]

[DOI]

Mallika Rathore

Peter A. Milder

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Power Transfer Optimization for Triboelectric Nanogenerators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022

High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications.

[BibT_eX]

[DOI]

CoRR, 2022

Wireless Power Transfer for Smart Knee Implants.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Session details: Session 2B: Computer-Aided Design (CAD).

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Error Probability Models for Voltage-Scaled Multiply-Accumulate Units.

[BibT_eX]

[DOI]

Mallika Rathore

Peter A. Milder

IEEE Trans. Very Large Scale Integr. Syst., 2020

Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Establishing a Covert Communication Channel in RF and mm-Wave Circuits.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current.

[BibT_eX]

[DOI]

Yongwan Park

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

AC Computing Methodology for RF-Powered IoT Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

SLECTS: Slew-Driven Clock Tree Synthesis.

[BibT_eX]

[DOI]

Savithri Sundareswaran

Benjamin Huang

IEEE Trans. Very Large Scale Integr. Syst., 2019

Frontend Electronic System for Triboelectric Harvester in a Smart Knee Implant.

[BibT_eX]

[DOI]

Manav Jain

Alwathiqbellah Ibrahim

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability.

[BibT_eX]

[DOI]

Tasnuva Noor

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Power and Data Integrity in Monolithic 3D Integrated SIMON Core.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Signal Shaping at Interface of Wireless Power Harvesting and AC Computational Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low Voltage Clock Tree Synthesis with Local Gate Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Ultra Low Power SIMON Core for Lightweight Encryption.

[BibT_eX]

[DOI]

Tutu Wan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits.

[BibT_eX]

[DOI]

Mallika Rathore

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Leveraging RF Power for Intelligent Tag Networks.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Package-embedded spiral inductor characterization with application to switching buck converters.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Perspective Paper - Can AC Computing Be an Alternative for Wirelessly Powered IoT Devices?

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2017

Open source cell library Mono3D to develop large-scale monolithic 3D integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

In-package spiral inductor characterization for high efficiency buck converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy efficient AC computing methodology for wirelessly powered IoT devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Routing Congestion Aware Cell Library Development for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Design Methodology for Voltage-Scaled Clock Distribution Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A new circuit design framework for IoT devices: Charge-recycling with wireless power harvesting.

[BibT_eX]

[DOI]

Tutu Wan

Milutin Stanacevic

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

On-chip hybrid regulator topology for portable SoCs with near-threshold operation.

[BibT_eX]

[DOI]

Yongwan Park

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploiting useful skew in gated low voltage clock trees.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Transistor-level camouflaged logic locking method for monolithic 3D IC security.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits.

[BibT_eX]

[DOI]

Milutin Stanacevic

IEEE Trans. Very Large Scale Integr. Syst., 2015

Quantifying the effect of local interconnects on on-chip power distribution.

[BibT_eX]

[DOI]

Peirong Ji

Microelectron. J., 2015

FinFET-Based Low-Swing Clocking.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Enhancing system-wide power integrity in 3D ICs with power gating.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Enhanced level shifter for multi-voltage operation.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Low swing TSV signaling using novel level shifters with single supply voltage.

[BibT_eX]

[DOI]

Shiwei Fang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A wirelessly powered system with charge recovery logic.

[BibT_eX]

[DOI]

Leo Filippini

Baris Taskin

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Novel Static D-Flip-Flop Topology for Low Swing Clocking.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs.

[BibT_eX]

[DOI]

Mohammad H. Asgari

Integr., 2014

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013

Power gating topologies in TSV based 3D integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Efficient characterization of TSV-to-transistor noise coupling in 3D ICs.

[BibT_eX]

[DOI]

Mohammad H. Asgari

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Effect of TSV fabrication technology on power distribution in 3D ICs.

[BibT_eX]

[DOI]

Suhas M. Satheesh

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2012

Power Distribution in TSV-Based 3-D Processor-Memory Stacks.

[BibT_eX]

[DOI]

Suhas M. Satheesh

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Design space exploration for robust power delivery in TSV based 3-D systems-on-chip.

[BibT_eX]

[DOI]

Suhas M. Satheesh

Proceedings of the IEEE 25th International SOC Conference, 2012

Methodology to determine dominant noise source in a system-on-chip based implantable device.

[BibT_eX]

[DOI]

Milutin Stanacevic

Proceedings of the IEEE 25th International SOC Conference, 2012

2011

Shielding Methodologies in the Presence of Power/Ground Noise.

[BibT_eX]

[DOI]

Selçuk Köse

IEEE Trans. Very Large Scale Integr. Syst., 2011

Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Compact substrate models for efficient noise coupling and signal isolation analysis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Methodology to achieve higher tolerance to delay variations in synchronous circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Contact merging algorithm for efficient substrate noise analysis in large scale circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Pseudo-random clocking to enhance signal integrity.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Input port reduction for efficient substrate extraction in large scale IC's.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Equivalent rise time for resonance in power/ground noise estimation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Substrate Noise Reduction Based On Noise Aware Cell Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Substrate and Ground Noise Interactions in Mixed-Signal Circuits.

[BibT_eX]

[DOI]