Emre Ozer
Affiliations:- Pragmatic Semiconductor, Cambridge, UK
- Arm Ltd., Cambridge, UK (former)
- Trinity College Dublin, Ireland (former)
- North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, NC, USA (former, PhD 2001)
According to our database1,
Emre Ozer
authored at least 41 papers
between 1998 and 2023.
Collaborative distances:
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Bibliography
2023
2018
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture.
IEEE Des. Test, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
2017
A "high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
2016
Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT.
IEEE Micro, 2016
IEEE Comput. Archit. Lett., 2016
Predicting room occupancy with a single passive infrared (PIR) sensor through behavior extraction.
Proceedings of the 2016 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2016
A Triple Core Lock-Step (TCLS) ARM® Cortex®-R5 Processor for Safety-Critical and Ultra-Reliable Applications.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
2015
On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015
An integrated SoC for science data processing in next-generation space flight instruments avionics.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Designing a SoC to control the next-generation space exploration flight science instruments.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2013
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
2009
Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
A stochastic bitwidth estimation technique for compact and low-power custom processors.
ACM Trans. Embed. Comput. Syst., 2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2008
2007
Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.
Proceedings of the Advances in Computer Systems Architecture, 2007
2006
Analyzing Effects of Trace Cache Configurations on the Prediction of Indirect Branches.
J. Instr. Level Parallelism, 2006
Low-Cost Microarchitectural Techniques for Enhancing the Prediction of Return Addresses on High-Performance Trace Cache Processors.
Proceedings of the Computer and Information Sciences, 2006
Proceedings of the 2006 International Conference on Compilers, 2006
Proceedings of the Architecture of Computing Systems, 2006
2005
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm.
IEEE Trans. Parallel Distributed Syst., 2005
Des. Autom. Embed. Syst., 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2004
Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power Using Optimizing Compiler Techniques.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors.
Proceedings of the Compiler Construction, 13th International Conference, 2004
2001
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001
1998
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998