Emmanuelle Encrenaz-Tiphène

According to our database, Emmanuelle Encrenaz-Tiphène authored at least 24 papers between 1995 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes.

Inès Ben El Ouahma, Quentin L. Meunier, Karine Heydemann, Emmanuelle Encrenaz

Proceedings of the PROOFS 2017, 2017

2015

Efficient Design and Evaluation of Countermeasures against Fault Attacks Using Formal Verification.

Lucien Goubet, Karine Heydemann, Emmanuelle Encrenaz, Ronald De Keulenaer

Proceedings of the Smart Card Research and Advanced Applications, 2015

2014

FSM-based properties and abstraction of components.

Syed Hussein Syed Alwi, Emmanuelle Encrenaz

Proceedings of the 25nd IEEE International Symposium on Rapid System Prototyping, 2014

Mutation Based Feature Localization.

Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey

Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014

Experimental evaluation of two software countermeasures against fault attacks.

Nicolas Moro, Karine Heydemann, Amine Dehbaoui, Bruno Robisson, Emmanuelle Encrenaz

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013

Electromagnetic Fault Injection: Towards a Fault Model on a 32-bit Microcontroller.

Nicolas Moro, Amine Dehbaoui, Karine Heydemann, Bruno Robisson, Emmanuelle Encrenaz

Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013

Assisting refinement in System-on-Chip design.

Hocine Mokrani, Rabéa Ameur-Boulifa, Emmanuelle Encrenaz-Tiphène

Proceedings of the 2013 Forum on specification and Design Languages, 2013

Verification of heterogeneous systems: Theory and industrial experiences.

Christoph Grimm, Emmanuelle Encrenaz

Proceedings of the 2013 Forum on specification and Design Languages, 2013

A Formally Verified Static Hypervisor with Hardware Support for a Many-Core Chip.

Geoffrey Plouviez, Emmanuelle Encrenaz, Franck Wajsbürt

Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

2012

Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process.

Syed Hussein Syed Alwi, Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

An efficient refinement strategy exploiting component properties in a cegar process.

Syed Hussein Syed Alwi, Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2010

A Polynomial Algorithm to Prove Deadlock-Freeness of Wormhole Networks.

Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux

Proceedings of the 18th Euromicro Conference on Parallel, 2010

Formal Verification of Timed VHDL Programs.

Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault

Proceedings of the 2010 Forum on specification & Design Languages, 2010

2009

Complementary Formal Approaches for Dependability Analysis.

Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2007

Using CTL formulae as component abstraction in a design and verification flow.

Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006

Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter.

Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip.

Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.

Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2006

2003

CTL May Be Ambiguous When Model Checking Moore Machines.

Cédric Roux, Emmanuelle Encrenaz

Proceedings of the Correct Hardware Design and Verification Methods, 2003

Design Validation of ZCSP with SPIN.

Vincent Beaudenon, Emmanuelle Encrenaz, Jean Lou Desbarbieux

Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

2002

Data Decision Diagrams for Petri Net Analysis.

Jean-Michel Couvreur, Emmanuelle Encrenaz, Emmanuel Paviot-Adet, Denis Poitrenaud, Pierre-André Wacrenier

Proceedings of the Applications and Theory of Petri Nets 2002, 2002

1998

Modular model checking of VLSI designs described in VHDL.

Fahim Rahim-Sarwary, Emmanuelle Encrenaz, Michel Minoux, Rajesh K. Bawa

Proceedings of the Computers and Their Applications (CATA-98), 1998

1996

A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis.

Rajesh K. Bawa, Emmanuelle Encrenaz

Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1996

1995

A Symbolic Relation for a Subset of VHDL'87 Descriptions and its Application to Symbolic Model Checking.

Emmanuelle Encrenaz

Proceedings of the Correct Hardware Design and Verification Methods, 1995