Emmanuel Boutillon

Andreas Burg

Chuan Zhang

IEEE Trans. Signal Process., 2024

2023

The Syndrome Bit Flipping Algorithm for LDPC Codes.

[BibT_eX]

[DOI]

Fakhreddine Ghaffari

IEEE Commun. Lett., July, 2023

Forward Backward Syndrome Computation: A Reduced Complexity CRC Code Decoder.

[BibT_eX]

[DOI]

IEEE Commun. Lett., May, 2023

Real-time energy-efficient software and hardware implementations of a QCSP communication system.

[BibT_eX]

[DOI]

Camille Monière

Bertrand Le Gal

J. Syst. Archit., 2023

Weighted Coherent Detection of QCSP frames.

[BibT_eX]

[DOI]

Luis Camacho

Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

The Best, the Requested, and the Default Elementary Check Node for EMS NB-LDPC Decoder.

[BibT_eX]

[DOI]

Joseph Jabour

Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

Buffers optimization for multi-core decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Wireless Communications and Networking Conference, 2023

Design of Concatenated Product Codes with Spatially-Coupled LDPC Codes.

[BibT_eX]

[DOI]

Yuqing Ren

Yifei Shen

Alexios Balatsoukas-Stimming

Andreas Burg

Proceedings of the 19th International Symposium on Wireless Communication Systems, 2023

Turbo-XZ Algorithm: Low-Latency Decoders for Quantum LDPC Codes.

[BibT_eX]

[DOI]

Nithin Raveendran

Bane Vasic

Proceedings of the 12th International Symposium on Topics in Coding, 2023

Rate-Adaptive Cyclic Complex Spreading Sequence for Non-Binary Decoders.

[BibT_eX]

[DOI]

Alexandru-Liviu Olteanu

Proceedings of the 12th International Symposium on Topics in Coding, 2023

Asymmetrical Extended Min-Sum for Successive Cancellation Decoding of Non-Binary Polar Codes.

[BibT_eX]

[DOI]

Joseph Jabour

Proceedings of the 12th International Symposium on Topics in Coding, 2023

C4-Sequences: Rate Adaptive Coded Modulation for Few Bits Message.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Topics in Coding, 2023

2022

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2022

Short Frame Transmission at Very Low SNR by Associating CCSK Modulation With NB-Code.

[BibT_eX]

[DOI]

IEEE Trans. Wirel. Commun., 2022

Integer Ring Sieve for Constructing Compact QC-LDPC Codes With Girths 8, 10, and 12.

[BibT_eX]

[DOI]

Alireza Tasdighi

IEEE Trans. Inf. Theory, 2022

Corrections to "Optimization of Non-Binary Parity Check Coefficients".

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2022

Phase Synchronization for Non-Binary Coded CCSK Short Frames.

[BibT_eX]

[DOI]

Proceedings of the 95th IEEE Vehicular Technology Conference, 2022

Efficient Software and Hardware Implementations of a QCSP Communication System.

[BibT_eX]

[DOI]

Camille Monière

Bertrand Le Gal

Proceedings of the Design and Architecture for Signal and Image Processing, 2022

2021

Sign-Preserving Min-Sum Decoders.

[BibT_eX]

[DOI]

Franklin Cochachin

David Declercq

IEEE Trans. Commun., 2021

Time-Synchronization of CCSK Short Frames.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Wireless and Mobile Computing, 2021

Time sliding window for the detection of CCSK frames.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Parallel CN-VN processing for NB-LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

The Best, The Requested, and The Default Non-Binary LDPC Decoding Algorithm.

[BibT_eX]

[DOI]

Joseph Jabour

Proceedings of the 11th International Symposium on Topics in Coding, 2021

Revisiting augmented decoding techniques for LTE Turbo Codes.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Topics in Coding, 2021

Rate-adaptive Inner Code for Non-Binary Decoders.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Topics in Coding, 2021

2020

Extended Barrel-Shifter for Versatile QC-LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Wirel. Commun. Lett., 2020

Revisiting the Max-Log-Map Algorithm With SOVA Update Rules: New Simplifications for High-Radix SISO Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2020

Integer Ring Sieve (IRS) for Constructing Compact QC-LDPC Codes with Large Girth.

[BibT_eX]

[DOI]

Alireza Tasdighi

CoRR, 2020

A Low-Complexity Dual Trellis Decoding Algorithm for High-Rate Convolutional Codes.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

2019

Editor's Note: Special Issue on Design and Implementation of Signal Processing Systems.

[BibT_eX]

[DOI]

Andreas Burg

J. Signal Process. Syst., 2019

Optimization of Non Binary Parity Check Coefficients.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2019

Additive, Structural, and Multiplicative Transformations for the Construction of Quasi-Cyclic LDPC Matrices.

[BibT_eX]

[DOI]

Alban Derrien

Audrey Cerqueus

IEEE Trans. Commun., 2019

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Hybrid Check Node Architectures for NB-LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Parallel Generation of Most Reliable LLRs of a Non-Binary Symbol.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2019

Dual Trellis Construction for High-Rate Punctured Convolutional Codes.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Symposium on Personal, 2019

First-Then-Second Extrema Selection.

[BibT_eX]

[DOI]

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

Optimization of Sign-Preserving Noise-Aided Min-Sum Decoders with Density Evolution.

[BibT_eX]

[DOI]

Franklin Cochachin

David Declercq

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

2017

A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Extended-forward architecture for simplified check node processing in NB-LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Hardware error correction using local syndromes.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Density evolution thresholds for noise-against-noise min-sum decoders.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Personal, 2017

Energy aware Networks-on-Chip cortex inspired communication.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

2016

Improved Multiplierless Architecture for Header Detection in DVB-S2 Standard.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Pre-Sorted Forward-Backward NB-LDPC Check Node Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Improving the Performance of the Carrier Tracking Loop for GPS Receivers in Presence of Transient Errors due to PVT Variations.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Noise-aided gradient descent bit-flipping decoders approaching maximum likelihood decoding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

A new approach to optimise Non-Binary LDPC codes for coded modulations.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

NB-LDPC check node with pre-sorted input.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

On Signal Space Diversity for non binary coded modulation schemes.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Telecommunications, 2016

Demo: Localisation in a faulty digital GPS receiver.

[BibT_eX]

[DOI]

Arnaud Dion

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Novel method for improving performances of normalized MS decoder using WIMAX code.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Advanced Communication Systems and Information Security, 2016

2015

LDPC decoder architecture for DVB-S2 and DVB-S2X standards.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A new architecture for high throughput, low latency NB-LDPC check node processing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Personal, 2015

Reliable gold code generators for GPS receivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Syndrome based check node processing of high order NB-LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Telecommunications, 2015

Reducing the impact of internal upsets inside the correlation process in GPS Receivers.

[BibT_eX]

[DOI]

Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Reliable NCO carrier generators for GPS receivers.

[BibT_eX]

[DOI]

Mourad Dridi

Gopalakrishnan Sundararajan

Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

2014

Noisy Gradient Descent Bit-Flip Decoding for LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2014

Decoding LDPC Codes With Locally Maximum-Likelihood Binary Messages.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2014

Simplified Compression of Redundancy Free Trellis Sections in Turbo Decoder.

[BibT_eX]

[DOI]

José Luis Sánchez-Rojas

IEEE Commun. Lett., 2014

2013

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm.

[BibT_eX]

[DOI]

Ali Al Ghouwayel

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Non-Binary Low-Density Parity-Check coded Cyclic Code-Shift Keying.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

A polar-based demapper of 8PSK demodulation for DVB-S2 systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Non-binary coded CCSK and Frequency-Domain Equalization with simplified LLR generation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Personal, 2013

Muller C-element based Decoder (MCD): A decoder against transient faults.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A contribution to the reduction of the dynamic power dissipation in the turbo decoder.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2012

A space-time redundancy technique for embedded stochastic error correction.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Design and implementation of a near maximum likelihood decoder for Cortex codes.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

An LDPC decoding method for fault-tolerant digital logic.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Architecture and Finite Precision Optimization for Layered LDPC Decoders.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

A Systolic LLR Generation Architecture for Non-Binary LDPC Decoders.

[BibT_eX]

[DOI]

Ali Al Ghouwayel

IEEE Commun. Lett., 2011

Hardware efficiency versus error probability in unreliable computation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Efficient multiplierless architecture for frame synchronization in DVB-S2 standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Hardware Discrete Channel Emulator.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

A new single-error correction scheme based on self-diagnosis residue number arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A flexible implementation of a Global Navigation Satellite System (GNSS) receiver for on-board satellite navigation.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009

Quasi-maximum-likelihood detector based on geometrical diversification greedy intensification.

[BibT_eX]

[DOI]

Amor Nafkha

Christian Roland

IEEE Trans. Commun., 2009

Optimization of Data-Flow Computations Using Canonical TED Representation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A new performance evaluation metric for sub-optimal iterative decoders.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

High-Level Dataflow Transformations Using Taylor Expansion Diagrams.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Non-Binary LDPC Codes Defined Over the General Linear Group: Finite Length Design and Practical Implementation Issues.

[BibT_eX]

[DOI]

Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

Conflict resolution for pipelined layered LDPC decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

A Convolutional Code for On-chip Interconnect Crosstalk Reduction.

[BibT_eX]

[DOI]

Antoine Courtay

Johann Laurent

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders.

[BibT_eX]

[DOI]

Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Optimizing data flow graphs to minimize hardware implementation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Probability-Driven Simulated Annealing for Optimizing Digital FIR Filters.

[BibT_eX]

[DOI]

Christian Roland

Marc Sevaux

Proceedings of the Adaptive and Multilevel Metaheuristics, 2008

2007

Generic Description and Synthesis of LDPC Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2007

Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues.

[BibT_eX]

[DOI]

Catherine Douillard

Guido Montorsi

Proc. IEEE, 2007

Simplified Hardware Bit Correlator.

[BibT_eX]

[DOI]

Christophe Cunat

IEEE Commun. Lett., 2007

Toward a Hardware Real Time SIMO Channel Emulator.

[BibT_eX]

[DOI]

Paul Chatellier

Patrick Tortelier

Proceedings of the Third IEEE International Conference on Wireless and Mobile Computing, 2007

Coarse Self-Synchronization Technique for GNSS Receivers.

[BibT_eX]

[DOI]

Irene Masinjara Mahafeno

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Energy Efficient Turbo Decoder with Reduced State Metric Quantization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Data-flow transformations using Taylor expansion diagrams.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Efficient factorization of DSP transforms using taylor expansion diagrams.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Maximum Spread of D-Dimensional Multiple Turbo Codes.

[BibT_eX]

[DOI]

David Gnaedig

IEEE Trans. Commun., 2005

Design of Three-Dimensional Multiple Slice Turbo Codes.

[BibT_eX]

[DOI]

David Gnaedig

Michel Jézéquel

EURASIP J. Adv. Signal Process., 2005

On Multiple Slice Turbo Codes.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2005

DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context.

[BibT_eX]

[DOI]

Pierre Bomel

Nabil Abdelli

Eric Martin

Anne-Marie Fouilliart

Philippe Kajfasz

Proceedings of the Embedded Computer Systems: Architectures, 2005

A near-optimal multiuser detector for MC-CDMA systems using geometrical approach.

[BibT_eX]

[DOI]

Amor Nafkha

Christian Roland

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

High-Level Synthesis in Latency Insensitive System Methodology.

[BibT_eX]

[DOI]

Pierre Bomel

Nabil Abdelli

Eric Martin

Anne-Marie Fouilliart

Philippe Kajfasz

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Synchronization Processor Synthesis for Latency Insensitive Systems.

[BibT_eX]

[DOI]

Pierre Bomel

Eric Martin

Luis Fernando González Pérez

Proceedings of the 2005 Design, 2005

VLSI Architecture for the M Algorithm Suited for Detection and Source Coding Applications.

[BibT_eX]

[DOI]

Andrés David García García

Javier Eduardo González Villarruel

Reynaldo Félix Acuña

Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005

2004

Synthèse d'architecture pour la réalisation comportementale de l'algorithme MAP pour Turbo Décodeur.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2004

A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Variable ordering for taylor expansion diagrams.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003

VLSI architectures for the MAP algorithm.

[BibT_eX]

[DOI]

Warren J. Gross

P. Glenn Gulak

IEEE Trans. Commun., 2003

2002

Bit error rate calculation for a multiband non-coherent on-off keying demodulation.

[BibT_eX]

[DOI]

Frédéric Guilloud

Luis Fernando González Pérez

Jean-Luc Danger

Proceedings of the IEEE International Conference on Communications, 2002

High-level design verification using Taylor Expansion Diagrams: first results.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2000

A study of a suboptimal VLSI architecture for joint source-channel trellis coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Efficient FPGA implementation of Gaussian noise generator for communication channel emulation.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Simplified path metric updating in the M algorithm for VLSI implementation.

[BibT_eX]

[DOI]

Luis González

Proceedings of the IEEE International Conference on Acoustics, 2000

Trace back techniques adapted to the surviving memory management in the M algorithm.

[BibT_eX]

[DOI]

Luis González

Proceedings of the IEEE International Conference on Acoustics, 2000

1998

A VLSI decoder for a new type of constellations adapted to the Rayleigh Fading Channel.

[BibT_eX]

[DOI]

Jose Maria Uruñuela-Martinez

Wirel. Networks, 1998

Decoding of constellations matched to the Rayleigh fading channel.

[BibT_eX]

[DOI]

Jose Maria Uruñuela-Martinez

Nicolas Demassieux

Ann. des Télécommunications, 1998

1997

Algebraic tools to build modulation schemes for fading channels.

[BibT_eX]

[DOI]

Xavier Giraud

Jean-Claude Belfiore

IEEE Trans. Inf. Theory, 1997

1994

A Multi-Dimensional Interconnection Network for SIMD Architectures.

[BibT_eX]

[DOI]

Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

Access and alignment of arrays for a bidimensional parallel memory.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors, 1994

1993

A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders.

[BibT_eX]