Emily Shriver

Orcid: 0009-0003-2135-6428

According to our database1, Emily Shriver authored at least 13 papers between 2002 and 2024.

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Bibliography

2024
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
Similarity-Based Fast Analysis of Data Center Networks.
IEEE Des. Test, December, 2023

MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2020
SimTrace: Capturing over Time Program Phase Behavior.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019
Hardware-Assisted Cross-Generation Prediction of GPUs Under Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Application Performance Prediction and Optimization Under Cache Allocation Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017
GPU Performance Estimation using Software Rasterization and Machine Learning.
ACM Trans. Embed. Comput. Syst., 2017

P<sup>4</sup>: Phase-based power/performance prediction of heterogeneous systems via neural networks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Statistical quality modeling of approximate hardware.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2012
A hybrid and adaptive model for predicting register file and SRAM power using a reference design.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2008
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

2002
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002


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