Emeric de Foucauld

Orcid: 0000-0001-8710-941X

According to our database1, Emeric de Foucauld authored at least 22 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2019
A 433-MHz SOI CMOS Automatic Impedance Matching Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

New design of analog and mixed-signal cells using back-gate cross-coupled structure.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2017
Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology.
J. Low Power Electron., 2016

UTBB-FDSOI complementary logic for high quality analog signal processing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Built-in test of millimeter-Wave circuits based on non-intrusive sensors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors.
J. Electron. Test., 2015

Balancing test cost reduction vs. measurements accuracy at test time.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014
Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop.
J. Low Power Electron., 2014

VCO design in SOI technologies.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Robust BER estimator for DBPSK modulation.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Cost-driven statistical analysis for selection of alternative measurements of analog circuits.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2012
A frequency measurement BIST implementation targeting gigahertz application.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
A Novel Method for Synthesizing an Automatic Matching Network and Its Control Unit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design of a RF matching network based on a new tunable inductor concept.
Microelectron. J., 2011

An antenna-filter codesign for cardiac implants.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
A Fast and Accurate Automatic Matching Network Designed for Ultra Low Power Medical Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A power optimized transconductance amplifier and its application to a 6<sup>th</sup> order lowpass GmC filter.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology.
Microelectron. J., 2008

Utilization of MEMS Tunable Inductors in the design of RF voltage-controlled oscillators.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.
Proceedings of the ESSCIRC 2008, 2008

2005
VHDL-AMS modeling of a multi-standard phase locked loop.
Proceedings of the 12th IEEE International Conference on Electronics, 2005


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