Emanuele Valea

According to our database, Emanuele Valea authored at least 23 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Hardware Implementation and Security Analysis of Local-Masked NTT for CRYSTALS-Kyber.

Rafael Carrera Rodriguez, Emanuele Valea, Florent Bruguier, Pascal Benoit

IACR Cryptol. ePrint Arch., 2024

Hardware Accelerator for FIPS 202 Hash Functions in Post-Quantum Ready SoCs.

Diamante Simone Crescenzo, Rafael Carrera Rodriguez, Riccardo Alidori, Florent Bruguier, Emanuele Valea, Pascal Benoit, Alberto Bosio

Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs.

Juan Suzano, Antoine Chastand, Emanuele Valea, Giorgio Di Natale, Anthony Philippe, Fady Abouzeid, Philippe Roche

Proceedings of the IEEE European Test Symposium, 2024

2023

Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems.

Jean-Philippe Noël, Emanuele Valea, Laurent Grenouillet, B. Chapuis, C. Fisher, A. Recoquillay, Bastien Giraud

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

2022

Correlation Electromagnetic Analysis on an FPGA Implementation of CRYSTALS-Kyber.

Rafael Carrera Rodriguez, Florent Bruguier, Emanuele Valea, Pascal Benoit

IACR Cryptol. ePrint Arch., 2022

Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions.

Michele Portolan, Emanuele Valea, Paolo Maistri, Giorgio Di Natale

IEEE Des. Test, 2022

Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.

Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea

Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

2021

Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks.

Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea

IEEE Access, 2021

Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design.

Davide Bellizia, Nadia El Mrabet, Apostolos P. Fournaris, Simon Pontié, Francesco Regazzoni, François-Xavier Standaert, Élise Tasso, Emanuele Valea

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Evaluating the Code Encryption Effects on Memory Fault Resilience.

Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea

Proceedings of the IEEE Latin-American Test Symposium, 2020

A Secure Scan Controller for Protecting Logic Locking.

Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.

Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network.

Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

Stream vs block ciphers for scan encryption.

Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre

Microelectron. J., 2019

A Survey on Security Threats and Countermeasures in IEEE Test Standards.

Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre

IEEE Des. Test, 2019

SECCS: SECure Context Saving for IoT Devices.

Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre

CoRR, 2019

A Comprehensive Approach to a Trusted Test Infrastructure.

Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale

Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

Providing Confidentiality and Integrity in Ultra Low Power IoT Devices.

Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Encryption-Based Secure JTAG.

Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

Encryption of test data: which cipher is better?

Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A New Secure Stream Cipher for Scan Chain Encryption.

Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

SI ECCS: SECure context saving for IoT devices.

Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

On the optimization of SBST test program compaction.

R. Cantora, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Emanuele Valea

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017