Emanuele Del Sozzo

Orcid: 0000-0003-3101-8118

According to our database1, Emanuele Del Sozzo authored at least 47 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs.
ACM Trans. Reconfigurable Technol. Syst., June, 2024

Starlight: A kernel optimizer for GPU processing.
J. Parallel Distributed Comput., May, 2024

Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2024

2023
Faber: A Hardware/SoftWare Toolchain for Image Registration.
IEEE Trans. Parallel Distributed Syst., 2023

An Energy-Efficient Domain-Specific Architecture for Regular Expressions.
IEEE Trans. Emerg. Top. Comput., 2023

Pushing the Level of Abstraction of Digital System Design: A Survey on How to Program FPGAs.
ACM Comput. Surv., 2023

New Solution For a (Scaff)Old Problem: an FPGA Approach.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Novel Union-Find-based Decoders for Scalable Quantum Error Correction on Systolic Arrays.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2023

Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
On the Automation of Radiomics-Based Identification and Characterization of NSCLC.
IEEE J. Biomed. Health Informatics, 2022

A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model.
IEEE Trans. Computers, 2022

Surfing the Wavefront of Genome Alignment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Large Forests and Where to "Partially" Fit Them.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.
ACM Trans. Reconfigurable Technol. Syst., 2021

CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching.
ACM Trans. Embed. Comput. Syst., 2021

Expertise and trade-offs in competence transfer from academia to industry: a successful case study.
Proceedings of the 6th IEEE International Forum on Research and Technology for Society and Industry, 2021

A Framework for Customizable FPGA-based Image Registration Accelerators.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Exploiting Heterogeneous Architectures for Rigid Image Registration.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
A CAD-based methodology to optimize HLS code via the Roofline model.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

SmartBlackBox: Enhancing Driver's Safety Via Real-Time Machine Learning on IoT Insurance Black-Boxes.
Proceedings of the IEEE Global Conference on Artificial Intelligence and Internet of Things, 2020

2019
On how to effectively target FPGAs from domain specific tools.
PhD thesis, 2019

Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based Systems.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Tiramisu: A Polyhedral Compiler for Expressing Fast and Portable Code.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

Towards an Automatic Imaging Biopsy of Non-Small Cell Lung Cancer.
Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019

Speeding Up Resting State Networks Recognition via a Hardware Accelerator.
Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019

2018
Automating Lung Cancer Identification in PET/CT Imaging.
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018

OXiGen: A Tool for Automatic Acceleration of C Functions Into Dataflow FPGA-Based Kernels.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

A Scalable FPGA Design for Cloud N-Body Simulation.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

A Unified Backend for Targeting FPGAs from DSLs.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

FPGA-based PairHMM Forward Algorithm for DNA Variant Calling.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Five-point algorithm: An efficient cloud-based FPGA implementation.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Highly Scalable and Efficient Parallel Design of N-Body Simulation on FPGA.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

A Common Backend for Hardware Acceleration on FPGA.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Software implementation and hardware acceleration of retinal vessel segmentation for diabetic retinopathy screening tests.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Using just-in-time code generation for transparent resource management in heterogeneous systems.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

Hardware Design Automation of Convolutional Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

On the Automation of High Level Synthesis of Convolutional Neural Networks.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Workload-aware power optimization strategy for asymmetric multiprocessors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016


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