Elyse Rosenbaum

Orcid: 0000-0002-3919-9833

According to our database1, Elyse Rosenbaum authored at least 51 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to electrostatic discharge reliability of integrated circuits".

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Reduced RC Time Constant High Voltage Tolerant Supply Clamp for ESD Protection in 16nm FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

On-Chip Single-Shot Pulse Generator for TDDB Characterization on a Sub-Nanosecond Timescale.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Collector Engineering of ESD PNP in BCD Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Semantic Autoencoder for Modeling BEOL and MOL Dielectric Lifetime Distributions.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Input-to-State Stable Neural Ordinary Differential Equations with Applications to Transient Modeling of Circuits.
Proceedings of the Learning for Dynamics and Control Conference, 2022

A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
Neural Networks for Transient Modeling of Circuits : Invited Paper.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

Considerations in High Voltage Lateral ESD PNP Design.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Compact Model of ESD Diode Suitable for Subnanosecond Switching Transients.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD.
IEEE Trans. Circuits Syst., 2020

Model-Augmented Conditional Mutual Information Estimation for Feature Selection.
Proceedings of the Thirty-Sixth Conference on Uncertainty in Artificial Intelligence, 2020

An Interpretable Predictive Model for Early Detection of Hardware Failure.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Sub-nanosecond Reverse Recovery Measurement for ESD Devices.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Model-Augmented Nearest-Neighbor Estimation of Conditional Mutual Information for Feature Selection.
CoRR, 2019

Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Stochastic modeling of air electrostatic discharge parameters.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
A Study of BER-Optimal ADC-Based Receiver for Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Full-Component Modeling and Simulation of Charged Device Model ESD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Compact distributed multi-finger MOSFET model for circuit-level ESD simulation.
Microelectron. Reliab., 2016

2015
Improved GGSCR layout for overshoot reduction.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2012
FEC-based 4 Gb/s backplane transceiver in 90nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
CDM-ESD induced damage in components using stacked-die packaging.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

ESD protection networks for 3D integrated circuits.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009
A new compact model for external latchup.
Microelectron. Reliab., 2009

Moving signals on and off chip.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
UVeriESD: An ESD verification tool for SoC design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications.
IEEE J. Solid State Circuits, 2007

2006
An automated and efficient substrate noise analysis tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Compact modeling of on-chip ESD protection devices using Verilog-A.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An 8-mW, ESD-protected, CMOS LNA for Ultra-Wideband Applications.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Comprehensive ESD protection for RF inputs.
Microelectron. Reliab., 2005

On-chip ESD protection for RF I/Os: devices, circuits and models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Critical evaluation of SOI design guidelines.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Noise characterization of static CMOS gates.
Proceedings of the 41th Design Automation Conference, 2004

2003
Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation.
Microelectron. Reliab., 2003

A Verilog-A compact model for ESD protection NMOSTs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A critical look at design guidelines for SOI logic gates.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Comprehensive frequency-dependent substrate noise analysis using boundary element methods.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions.
Microelectron. Reliab., 2001

Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits.
Microelectron. Reliab., 2001

Trap generation and breakdown processes in very thin gate oxides.
Microelectron. Reliab., 2001

2000
Interconnect thermal modeling for accurate simulation of circuittiming and reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
Interconnect thermal modeling for determining design limits on current density.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation.
Proceedings of the 36th Conference on Design Automation, 1999

1998
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
iTEM: a temperature-dependent electromigration reliability diagnosis tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.
Proceedings of the 33st Conference on Design Automation, 1996

iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.
Proceedings of the 33st Conference on Design Automation, 1996

1993
Berkeley reliability tools-BERT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993


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