Elizabeth J. Brauer
According to our database1,
Elizabeth J. Brauer
authored at least 19 papers
between 1993 and 2009.
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Collaborative distances:
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2009
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.
Microelectron. J., 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2004
Finding efficient inductor geometries in digital CMOS process for RF applications.
Proceedings of the Second IASTED International Conference on Circuits, 2004
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.
Proceedings of the Second IASTED International Conference on Circuits, 2004
Low noise MCML prefix adders using 0.18 µm CMOS technology.
Proceedings of the Second IASTED International Conference on Circuits, 2004
1999
Proceedings of the International Joint Conference Neural Networks, 1999
1998
VLSI Design, 1998
1997
Proceedings of International Conference on Neural Networks (ICNN'97), 1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1993
Functional Verification of ECL Circuits Including Voltage Regulators.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993