Elio Consoli
According to our database1,
Elio Consoli
authored at least 27 papers
between 2009 and 2015.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2015
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Comparative analysis of the robustness of master-slave flip-flops against variations.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.
IEEE Trans. Very Large Scale Integr. Syst., 2014
2013
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions.
IEEE J. Solid State Circuits, 2013
2012
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2012
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Int. J. Circuit Theory Appl., 2012
Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
EChO power management unit with reconfigurable switched-capacitor converter in 65 nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009