Elif Bilge Kavun

Orcid: 0000-0003-3193-8440

Affiliations:
  • University of Passau, Germany
  • Ruhr University Bochum, Germany (PhD 2015)


According to our database1, Elif Bilge Kavun authored at least 38 papers between 2010 and 2024.

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Bibliography

2024
NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V.
Cryptogr., March, 2024

Secure Data-Binding in FPGA-based Hardware Architectures utilizing PUFs.
Proceedings of the 19th ACM Asia Conference on Computer and Communications Security, 2024

2023
PUF-Phenotype: A Robust and Noise-Resilient Approach to Aid Group-Based Authentication With DRAM-PUFs Using Machine Learning.
IEEE Trans. Inf. Forensics Secur., 2023

Practical Non-Invasive Probing Attacks Against Novel Carbon-Nanotube-Based Physical Unclonable Functions.
CoRR, 2023

Design Rationale for Symbiotically Secure Key Management Systems in IoT and Beyond.
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023

An Evaluation of the Security and the Privacy of a Novel Single Sign-On System Based on Physical Unclonable Functions.
Proceedings of the 13th IEEE International Conference on Consumer Electronics - Berlin, 2023

Invited Paper: A Scalable Hardware/Software Co-Design Approach for Efficient Polynomial Multiplication.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

A Privacy-Preserving Protocol Level Approach to Prevent Machine Learning Modelling Attacks on PUFs in the Presence of Semi-Honest Verifiers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

A Generic Obfuscation Framework for Preventing ML-Attacks on Strong-PUFs through Exploitation of DRAM-PUFs.
Proceedings of the 8th IEEE European Symposium on Security and Privacy, 2023

Spatial Correlation in Weak Physical Unclonable Functions: A Comprehensive Overview.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

A Modular Open-Source Cryptographic Co-Processor for Internet of Things.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Analyzing ModuloNET Against Transition Effects.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

Performance Comparison of Post-Quantum Signature Algorithms Through An Android Email Application Plug-in.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023

2022
PUF-Phenotype: A Robust and Noise-Resilient Approach to Aid Intra-Group-based Authentication with DRAM-PUFs Using Machine Learning.
CoRR, 2022

A Power Reduction Technique Based on Linear Transformations for Block Ciphers.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Identification and Classification of Corrupted PUF Responses via Machine Learning.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Evaluating Cryptographic Extensions On A RISC-V Simulation Environment.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Deep Learning Techniques for Side-Channel Analysis on AES Datasets Collected from Hardware and Software Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

2020
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs.
IACR Cryptol. ePrint Arch., 2019

Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

2018
A Survey on Authenticated Encryption-ASIC Designer's Perspective.
ACM Comput. Surv., 2018

2015
Resource-efficient cryptography for ubiquitous computing.
PhD thesis, 2015

2014
Large-scale high-resolution computational validation of novel complexity models in linear cryptanalysis.
J. Comput. Appl. Math., 2014

Block Ciphers - Focus On The Linear Layer (feat. PRIDE): Full Version.
IACR Cryptol. ePrint Arch., 2014

Block Ciphers - Focus on the Linear Layer (feat. PRIDE).
Proceedings of the Advances in Cryptology - CRYPTO 2014, 2014

2013
Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures.
IACR Cryptol. ePrint Arch., 2013

A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A Non-Linear/Linear Instruction Set Extension for Lightweight Ciphers.
Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012
PRINCE - A Low-latency Block Cipher for Pervasive Computing Applications (Full version).
IACR Cryptol. ePrint Arch., 2012

IPSecco: A lightweight and reconfigurable IPSec core.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

On the Implementation Aspects of Sponge-Based Authenticated Encryption for Pervasive Devices.
Proceedings of the Smart Card Research and Advanced Applications, 2012

PRINCE - A Low-Latency Block Cipher for Pervasive Computing Applications - Extended Abstract.
Proceedings of the Advances in Cryptology - ASIACRYPT 2012, 2012

2011
RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Memory Encryption for Smart Cards.
Proceedings of the Smart Card Research and Advanced Applications, 2011

2010
A Lightweight Implementation of Keccak Hash Function for Radio-Frequency Identification Applications.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2010

A pipelined camellia architecture for compact hardware implementation.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010


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