Elham K. Moghaddam

Orcid: 0000-0001-8697-9544

According to our database1, Elham K. Moghaddam authored at least 20 papers between 2007 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Time and Area Optimized Testing of Automotive ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2019
Logic BIST With Capture-Per-Clock Hybrid Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Test Time and Area Optimized BrST Scheme for Automotive ICs.
Proceedings of the IEEE International Test Conference, 2019

2018
Hardware Protection via Logic Locking Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Embedded Deterministic Test Points.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
On New Test Points for Compact Cell-Aware Tests.
IEEE Des. Test, 2016

Test point insertion in hybrid test compression/LBIST architectures.
Proceedings of the 2016 IEEE International Test Conference, 2016

Minimal area test points for deterministic patterns.
Proceedings of the 2016 IEEE International Test Conference, 2016

On Test Points Enhancing Hardware Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Isometric Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Embedded deterministic test points for compact cell-aware tests.
Proceedings of the 2015 IEEE International Test Conference, 2015

Design for low test pattern counts.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Isometric test compression with low toggling activity.
Proceedings of the 2014 International Test Conference, 2014

2011
Low power compression utilizing clock-gating.
Proceedings of the 2011 IEEE International Test Conference, 2011

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power Aware Embedded Test.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
At-speed scan test with low switching activity.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Low capture power at-speed test in EDT environment.
Proceedings of the 2011 IEEE International Test Conference, 2010

2007
An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS Circuits.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits.
Proceedings of the 16th Asian Test Symposium, 2007


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