Eleonora Testa

According to our database, Eleonora Testa authored at least 25 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Scalable Sequential Optimization Under Observability Don't Cares.

Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2021

Three-Input Gates for Logic Synthesis.

Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

LUT-Based Optimization For ASIC Design Flow.

Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.

Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Data Structures and Algorithms for Logic Synthesis in Advanced Technologies.

Eleonora Testa

PhD thesis, 2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.

Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli

IACR Cryptol. ePrint Arch., 2020

Extending Boolean Methods for Scalable Logic Synthesis.

Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

IEEE Access, 2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).

Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Mapping Monotone Boolean Functions into Majority.

Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Winston Haaswijk, Giovanni De Micheli

IEEE Trans. Computers, 2019

Logic Synthesis for Established and Emerging Computing.

Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Giovanni De Micheli

Proc. IEEE, 2019

A Hybrid Method for Spectral Translation Equivalent Boolean Functions.

Mathias Soeken, Eleonora Testa, D. Michael Miller

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Logic Optimization of Majority-Inverter Graphs.

Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.

Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.

Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Pairs of majority-decomposing functions.

Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli

Inf. Process. Lett., 2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.

Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Majority logic synthesis.

Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken

Proceedings of the International Conference on Computer-Aided Design, 2018

Practical exact synthesis.

Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.

Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Classifying Functions with Exact Synthesis.

Winston Haaswijk, Eleonora Testa, Mathias Soeken, Giovanni De Micheli

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Wave pipelining for majority-based beyond-CMOS technologies.

Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Multi-level logic benchmarks: An exactness study.

Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Inversion optimization in Majority-Inverter Graphs.

Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016