Elena I. Vatajelu
Orcid: 0000-0002-4588-1812
According to our database1,
Elena I. Vatajelu
authored at least 72 papers
between 2010 and 2025.
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Bibliography
2025
SPICE-Level Demonstration of Unsupervised Learning With Spintronic Synapses in Spiking Neural Networks.
IEEE Access, 2025
2024
IEEE Des. Test, December, 2024
IEEE Des. Test, June, 2024
GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN Inference.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Study of a Spintronic-based STDP-trained SNN under Fabrication-induced Process Variability.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Proceedings of the IEEE European Test Symposium, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
J. Electron. Test., 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
State of the art and challenges for test and reliability of emerging nonvolatile resistive memories.
Int. J. Circuit Theory Appl., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
2017
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
2016
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
ACM J. Emerg. Technol. Comput. Syst., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial).
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
Integr., 2013
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.
Proceedings of the 15th European Test Symposium, 2010