Elena Dubrova

Joel Gärtner

IACR Cryptol. ePrint Arch., 2024

Single-trace side-channel attacks on MAYO exploiting leaky modular multiplication.

[BibT_eX]

[DOI]

Sönke Jendral

IACR Cryptol. ePrint Arch., 2024

MAYO Key Recovery by Fixing Vinegar Seeds.

[BibT_eX]

[DOI]

Sönke Jendral

IACR Cryptol. ePrint Arch., 2024

Solving AES-SAT Using Side-Channel Hints: A Practical Assessment.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2024

Unpacking Needs Protection: A Single-Trace Secret Key Recovery Attack on Dilithium.

[BibT_eX]

[DOI]

IACR Commun. Cryptol., 2024

Breaking SCA-Protected CRYSTALS-Kyber with a Single Trace.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

A Single-Trace Fault Injection Attack on Hedged Module Lattice Digital Signature Algorithm (ML-DSA).

[BibT_eX]

[DOI]

Sönke Jendral

John Preuß Mattsson

Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2024

Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure.

[BibT_eX]

[DOI]

Can Aknesil

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

A Side-Channel Attack on a Higher-Order Masked CRYSTALS-Kyber Implementation.

[BibT_eX]

[DOI]

Proceedings of the Applied Cryptography and Network Security, 2024

2023

A side-channel attack on a masked and shuffled software implementation of Saber.

[BibT_eX]

[DOI]

Thomas Johansson

J. Cryptogr. Eng., November, 2023

FPGA Design Deobfuscation by Iterative LUT Modification at Bitstream Level.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., March, 2023

Single-Trace Side-Channel Attacks on CRYSTALS-Dilithium: Myth or Reality?

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

A Side-Channel Attack on a Bitsliced Higher-Order Masked CRYSTALS-Kyber Implementation.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

A Side-Channel Attack on a Masked Hardware Implementation of CRYSTALS-Kyber.

[BibT_eX]

[DOI]

Yanning Ji

IACR Cryptol. ePrint Arch., 2023

A Single-Trace Message Recovery Attack on a Masked and Shuffled Implementation of CRYSTALS-Kyber.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2023

A Near-Field EM Sensor Implemented in FPGA Configurable Fabric.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Trust, 2023

Higher-Order Boolean Masking Does Not Prevent Side-Channel Attacks on LWE/LWR-based PKE/KEMs.

[BibT_eX]

[DOI]

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

A side-channel resistant implementation of AES combining clock randomization with duplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Is Your FPGA Transmitting Secrets: Covert Antennas from Interconnect.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

A Shared Key Recovery Attack on a Masked Implementation of CRYSTALS-Kyber's Encapsulation Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Foundations and Practice of Security - 16th International Symposium, 2023

A Side-Channel Secret Key Recovery Attack on CRYSTALS-Kyber Using k Chosen Ciphertexts.

[BibT_eX]

[DOI]

Proceedings of the Codes, Cryptology and Information Security, 2023

Breaking a Fifth-Order Masked Implementation of CRYSTALS-Kyber by Copy-Paste.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Asia Public-Key Cryptography Workshop, 2023

Secret Key Recovery Attack on Masked and Shuffled Implementations of CRYSTALS-Kyber and Saber.

[BibT_eX]

[DOI]

Proceedings of the Applied Cryptography and Network Security Workshops, 2023

2022

Making Biased DL Models Work: Message and Key Recovery Attacks on Saber Using Amplitude-Modulated EM Emanations.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Side-Channel Analysis of Saber KEM Using Amplitude-Modulated EM Emanations.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Side-Channel Attacks on Lattice-Based KEMs Are Not Prevented by Higher-Order Masking.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

A Side-Channel Attack on a Hardware Implementation of CRYSTALS-Kyber.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Breaking a Fifth-Order Masked Implementation of CRYSTALS-Kyber by Copy-Paste.

[BibT_eX]

[DOI]

Joel Gärtner

IACR Cryptol. ePrint Arch., 2022

Side-Channel Attack Countermeasures Based On Clock Randomization Have a Fundamental Flaw.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Secret Key Recovery Attacks on Masked and Shuffled Implementations of CRYSTALS-Kyber and Saber.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers.

[BibT_eX]

[DOI]

Can Aknesil

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Message Recovery Attack on LWE/LWR-Based PKE/KEMs Using Amplitude-Modulated EM Emanations.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - ICISC 2022, 2022

Side-Channel Analysis of the Random Number Generator in STM32 MCUs.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Do Not Rely on Clock Randomization: A Side-Channel Attack on a Protected Hardware Implementation of AES.

[BibT_eX]

[DOI]

Proceedings of the Foundations and Practice of Security - 15th International Symposium, 2022

2021

A Side-Channel Attack on a Masked IND-CCA Secure Saber KEM Implementation.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Can Deep Learning Break a True Random Number Generator?

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Tandem Deep Learning Side-Channel Attack on FPGA Implementation of AES.

[BibT_eX]

[DOI]

SN Comput. Sci., 2021

Breaking Masked and Shuffled CCA Secure Saber KEM by Power Analysis.

[BibT_eX]

[DOI]

Thomas Johansson

IACR Cryptol. ePrint Arch., 2021

A Side-Channel Attack on a Masked IND-CCA Secure Saber KEM.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2021

An FPGA Implementation of 4×4 Arbiter PUF.

[BibT_eX]

[DOI]

Can Aknesil

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Advanced Far Field EM Side-Channel Attack on AES.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM on Cyber-Physical System Security Workshop, 2021

2020

Profiled Deep Learning Side-Channel Attack on a Protected Arbiter PUF Combined with Bitstream Modification.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Far Field EM Side-Channel Attack on AES Using Deep Learning.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Federated Learning in Side-Channel Analysis.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Tandem Deep Learning Side-Channel Attack Against FPGA Implementation of AES.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Bitstream Modification of Trivium.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Interconnect-Aware Bitstream Modification.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Bitstream Modification Attack on SNOW 3G.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Breaking ACORN at Bitstream Level.

[BibT_eX]

[DOI]

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

FPGA Bitstream Modification with Interconnect in Mind.

[BibT_eX]

[DOI]

Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

Multi-Source Training Deep-Learning Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Attacking Trivium at the Bitstream Level.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

How Deep Learning Helps Compromising USIM.

[BibT_eX]

[DOI]

Sebastian Forsmark

Proceedings of the Smart Card Research and Advanced Applications, 2020

2019

How Diversity Affects Deep-Learning Side-Channel Attacks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Breaking ACORN with a Single Fault.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Threshold Physical Unclonable Functions.

[BibT_eX]

[DOI]

Felipe S. Marranghello

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE European Symposium on Security and Privacy Workshops, 2019

2018

Message Authentication Based on Cryptographically Secure CRC without Polynomial Irreducibility Test.

[BibT_eX]

[DOI]

Cryptogr. Commun., 2018

One-Sided Countermeasures for Side-Channel Attacks Can Backfire.

[BibT_eX]

[DOI]

Felipe S. Marranghello

Victor Diges Teijeira

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

Lightweight Message Authentication for Constrained Devices.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

On Designing PUF-Based TRNGs with Known Answer Tests.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Comparison of CRC and KECCAK Based Message Authentication for Resource-Constrained Devices.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A Reconfigurable Arbiter PUF with 4 x 4 Switch Blocks.

[BibT_eX]

[DOI]

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017

Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

MVL-PUFs: multiple-valued logic physical unclonable functions.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

Espresso: A stream cipher for 5G wireless communication systems.

[BibT_eX]

[DOI]

Martin Hell

Cryptogr. Commun., 2017

TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices.

[BibT_eX]

[DOI]

Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, 2017

Temperature aware phase/frequency detector-basec RO-PUFs exploiting bulk-controlled oscillators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Physical Unclonable Functions based on Temperature Compensated Ring Oscillators.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

A SAT-Based Algorithm for Finding Short Cycles in Shift Register Based Stream Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Protecting IMSI and User Privacy in 5G Networks.

[BibT_eX]

[DOI]

Karl Norrman

Mats Näslund

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

Error-Correcting Message Authentication for 5G.

[BibT_eX]

[DOI]

Proceedings of the 9th EAI International Conference on Mobile Multimedia Communications, 2016

On Constructing Secure and Hardware-Efficient Invertible Mappings.

[BibT_eX]

[DOI]

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015

Lightweight CRC-based Message Authentication.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Cryptographically Secure CRC for Lightweight Message Authentication.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Remotely Managed Logic Built-In Self-Test for Secure M2M Communications.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Design of a terminal solution for integration of in-home health care devices and services towards the Internet-of-Things.

[BibT_eX]

[DOI]

Enterp. Inf. Syst., 2015

A Fast Heuristic Algorithm for Redundancy Removal.

[BibT_eX]

[DOI]

CoRR, 2015

A Linear-Time Algorithm for Finding All Double-Vertex Dominators of a Given Vertex.

[BibT_eX]

[DOI]

CoRR, 2015

Logic BIST: State-of-the-Art and Open Problems.

[BibT_eX]

[DOI]

CoRR, 2015

CRC-Based Message Authentication for 5G Mobile Technology.

[BibT_eX]

[DOI]

Mats Näslund

Göran Selander

Proceedings of the 2015 IEEE TrustCom/BigDataSE/ISPA, 2015

A scan partitioning algorithm for reducing capture power of delay-fault LBIST.

[BibT_eX]

[DOI]

Gunnar Carlsson

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A random access procedure based on tunable puzzles.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Conference on Communications and Network Security, 2015

2014

Area-efficient high-coverage LBIST.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

An Equivalence-Preserving Transformation of Shift Registers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Generation of full cycles by a composition of NLFSRs.

[BibT_eX]

[DOI]

Des. Codes Cryptogr., 2014

An new approach to reliable FSRs lDesign.

[BibT_eX]

[DOI]

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Evaluation of alternative LBIST flows: A case study.

[BibT_eX]

[DOI]

Gunnar Carlsson

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Energy-efficient message authentication for IEEE 802.15.4-based wireless sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Keyed logic BIST for Trojan detection in SoC.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

An Algorithm for Constructing a Minimal Register with Non-linear Update Generating a Given Sequence.

[BibT_eX]

[DOI]

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Secure and efficient LBIST for feedback shift register-based cryptographic systems.

[BibT_eX]

[DOI]

Mats Näslund

Göran Selander

Proceedings of the 19th IEEE European Test Symposium, 2014

Synthesis of power- and area-efficient binary machines for incompletely specified sequences.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A Scalable Method for Constructing Galois NLFSRs With Period 2<sup>n</sup>-1 Using Cross-Join Pairs.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2013

A BDD-Based Method for LFSR Parallelization with Application to Fast CRC Encoding.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2013

Embedding of Deterministic Test Data for In-Field Testing

[BibT_eX]

[DOI]

CoRR, 2013

An Algorithm for Constructing a Smallest Register with Non-Linear Update Generating a Given Binary Sequence.

[BibT_eX]

[DOI]

CoRR, 2013

An Improved Hardware Implementation of the Quark Hash Function.

[BibT_eX]

[DOI]

Proceedings of the Radio Frequency Identification, 2013

Secure Key Storage Using State Machines.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Protecting Ring Oscillator Physical Unclonable Functions Against Modeling Attacks.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - ICISC 2013, 2013

On-chip area-efficient binary sequence storage.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Faster Shift Register Alternative to Filter Generators.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Finding Attractors in Synchronous Multiple-Valued Networks Using SAT-based Bounded Model Checking.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2012

A Method for Generating Full Cycles by a Composition of NLFSRs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

A List of Maximum Period NLFSRs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

A BDD-Based Approach to Constructing LFSRs for Parallel CRC Encoding.

[BibT_eX]

[DOI]

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Power-security trade-off in multi-level power analysis countermeasures for FSR-based stream ciphers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An Improved Hardware Implementation of the Grain-128a Stream Cipher.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - ICISC 2012, 2012

Ring oscillator physical unclonable function with multi level supply voltages.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An Architectural Countermeasure against Power Analysis Attacks for FSR-Based Stream Ciphers.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

The Robustness of Balanced Boolean Networks.

[BibT_eX]

[DOI]

Proceedings of the Complex Networks, results of the 3rd Workshop on Complex Networks, 2012

2011

Synthesis of Binary Machines.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2011

A SAT-Based Algorithm for Finding Attractors in Synchronous Boolean Networks.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2011

AIG rewriting using 5-input cuts.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Synthesis of parallel binary machines.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A countermeasure against power analysis attacks for FSR-based stream ciphers.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Integrated logic synthesis using simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Finding matching initial states for equivalent NLFSRs in the Fibonacci and the Galois configurations.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2010

Synthesis of Binary k-Stage Machines

[BibT_eX]

[DOI]

CoRR, 2010

An Algorithm for Constructing a Fastest Galois NLFSR Generating a Given Sequence.

[BibT_eX]

[DOI]

Jean-Michel Chabloz

Proceedings of the Sequences and Their Applications - SETA 2010, 2010

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

An Improved Hardware Implementation of the Grain Stream Cipher.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

A transformation from the Fibonacci to the Galois NLFSRs.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 2009

An Improved Implementation of Grain

[BibT_eX]

[DOI]

CoRR, 2009

How to speed-up your NLFSR-based stream cipher.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A Computational Scheme Based on Random Boolean Networks.

[BibT_eX]

[DOI]

Trans. Comp. Sys. Biology, 2008

An equivalence preserving transformation from the Fibonacci to the Galois NLFSRs

[BibT_eX]

[DOI]

CoRR, 2008

Self-Organization for Fault-Tolerance.

[BibT_eX]

[DOI]

Proceedings of the Self-Organizing Systems, Third International Workshop, 2008

On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Bio-inspired fault-tolerance.

[BibT_eX]

[DOI]

Proceedings of the 3rd International ICST Conference on Bio-Inspired Models of Network, 2008

2007

Evaluation and Comparison of Threshold Logic Gates.

[BibT_eX]

[DOI]

Vasilios Lirigis

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

A computational model based on Random Boolean Networks.

[BibT_eX]

[DOI]

Proceedings of the 2nd International ICST Conference on Bio-Inspired Models of Network, 2007

2006

Random Multiple-Valued Networks: Theory and Applications.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Bound-Set Preserving ROBDD Variable Orderings May Not Be Optimum.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Kauffman networks: analysis and applications.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Computing attractors in dynamic networks.

[BibT_eX]

Proceedings of the AC 2005, 2005

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Structural Testing Based on Minimum Kernels.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Improved Boolean function hashing based on multiple-vertex dominators.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A fast algorithm for finding common multiple-vertex dominators in circuit graphs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Logic optimization using rule-based randomized search.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Probabilistic Equivalence Checking of Multiple-Valued Functions.

[BibT_eX]

[DOI]

Harald Sack

J. Multiple Valued Log. Soft Comput., 2004

A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

On relation between non-disjoint decomposition and multiple-vertex dominators.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Disjoint-support Boolean decomposition combining functional and structural methods.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Implementation of Multiple-Valued Functions Using Literal-Splitting Technique.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Boolean Decomposition Based on Cyclic Chains.

[BibT_eX]

[DOI]

Johan Karlsson

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A BDD-based fast heuristic algorithm for disjoint decomposition.

[BibT_eX]

[DOI]

Tomas Bengtsson

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Technology Mapping for Chemically Assembled Electronic Nanotechnology.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Fast Heuristic Algorithm for Disjunctive.

[BibT_eX]

Tomas Bengtsson

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

A Conjunctive Canonical Expansion of Multiple-Valued Functions.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Self-Checking 1-out-of-n CMOS Current-Mode Checker.

[BibT_eX]

[DOI]

Jimson Mathew

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Composition Trees in Finding Best Variable Orderings for ROBDDs.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.

[BibT_eX]

[DOI]

Imed Ben Dhaou

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'.

[BibT_eX]

[DOI]

Luca Macchiarulo

IEEE Trans. Computers, 2000

Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

TOP: An Algorithm for Three-Level Optimization of PLDs.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

1999

Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions.

[BibT_eX]

Harald Sack

Christoph Meinel

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Probabilistic Verification of Multiple-Valued Functions

[BibT_eX]

Harald Sack

Universität Trier, Mathematik/Informatik, Forschungsbericht, 1999

Evaluation of m-Valued Fixed Polarity Generalizations of Reed-Muller Canonical Form.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1997

Boolean and multiple-valued functions in combinational logic synthesis.

[BibT_eX]

[DOI]

PhD thesis, 1997

Finding Composition Trees for Multiple-Valued Functions.

[BibT_eX]

[DOI]

Bernhard von Stengel

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

1996

Testability of Generalized Multiple-Valued Reed-Muller Circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

The Evaluation of Full Sensitivity for Test Generation in MVL Circuits.

[BibT_eX]

[DOI]

Dilian Gurov

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits.

[BibT_eX]

[DOI]

Dilian Gurov