Elaheh Bozorgzadeh

Kanghee Kim

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

AFFIX: Automatic Acceleration Framework for FPGA Implementation of OpenVX Vision Algorithms.

[BibT_eX]

[DOI]

Sajjad Taheri

Payman Behnam

Alexandru Nicolau

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Communication-Computation co-Design of Decentralized Task Chain in CPS Applications.

[BibT_eX]

[DOI]

Seyyed Ahmad Razavi

Solmaz S. Kia

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

System Services for Reconfigurable Hardware Acceleration in Mobile Devices.

[BibT_eX]

[DOI]

Hsin-Yu Ting

Ardalan Amiri Sani

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Scalable Multi-Queue Data Transfer Scheme for FPGA-Based Multi-Accelerators.

[BibT_eX]

[DOI]

Siavash Rezaei

Kanghee Kim

César-Alejandro Hernández-Calderón

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Resource-Aware Decentralization of a UKF-Based Cooperative Localization for Networked Mobile Robots.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

2016

Data-rate-aware FPGA-based acceleration framework for streaming applications.

[BibT_eX]

[DOI]

Siavash Rezaei

Saeed Mirzamohammadi

Alex Nicolau

Michael J. Prather

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Harvesting-aware adaptive energy management in solar-powered embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Path selection and sensor insertion flow for age monitoring in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Aging-aware high-level physical planning for reconfigurable systems.

[BibT_eX]

[DOI]

Zana Ghaderi

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Modeling and control battery aging in energy harvesting systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Smart Grid Communications, 2015

Orchestrated application quality and energy storage management in solar-powered embedded systems.

[BibT_eX]

[DOI]

Hossein Tajik

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A Unified Stochastic Model for Energy Management in Solar-Powered Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Reconfiguration-Aware Task Graph Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Multi-level QoS Support with Variable Window Size in Weakly Hard Real-Time Systems.

[BibT_eX]

[DOI]

Moonju Park

Proceedings of the 2015 IEEE 3rd International Conference on Cyber-Physical Systems, 2015

2014

Distributed flow optimization control for energy-harvesting wireless sensor networks.

[BibT_eX]

[DOI]

Kiyoshi Nakayama

Lubomir F. Bic

Michael B. Dillencourt

Proceedings of the IEEE International Conference on Communications, 2014

2013

Transition-aware task scheduling and configuration selection in reconfigurable embedded systems.

[BibT_eX]

[DOI]

SIGBED Rev., 2013

Adapting data quality with multihop routing for energy harvesting wireless sensor networks.

[BibT_eX]

[DOI]

Mahnaz Roshanaei

Proceedings of the International Green Computing Conference, 2013

2012

QuARES: A quality-aware renewable energy-driven sensing framework.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2012

Hardware-Assisted Detection of Malicious Software in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

Energy Harvesting for Sustainable Smart Spaces.

[BibT_eX]

[DOI]

Adv. Comput., 2012

Energy Budget Management for Energy Harvesting Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Adaptable intrusion detection using partial runtime reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Minimization of Trojan footprint by reducing Delay/Area impact.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011

SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

On leakage power optimization in clock tree networks for ASICs and general-purpose processors.

[BibT_eX]

[DOI]

Houman Homayoun

Fadi J. Kurdahi

Sustain. Comput. Informatics Syst., 2011

Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010).

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

Process variation aware system-level load assignment for total energy minimization using stochastic ordering.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

QuARES: Quality-aware data collection in energy harvesting sensor networks.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Reconfiguration-aware real-time scheduling under QoS constraint.

[BibT_eX]

[DOI]

Deepak Mishra

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.

[BibT_eX]

[DOI]

Houman Homayoun

Fadi J. Kurdahi

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.

[BibT_eX]

[DOI]

Benjamin Carrión Schäfer

Kazutoshi Wakabayashi

Houman Homayoun

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Reconfiguration-aware spectrum sharing for FPGA based software defined radio.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Welcome message.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Transition-aware real-time task scheduling for reconfigurable embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

SEU-aware resource binding for modular redundancy based designs on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.

[BibT_eX]

[DOI]

Amir Hossein Gholamipour

Lichun Bao

Proceedings of the 26th International Conference on Computer Design, 2008

Process variation aware system-level task allocation using stochastic ordering of delay distributions.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.

[BibT_eX]

[DOI]

Sejong Oh

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Statistical power profile correlation for realistic thermal estimation.

[BibT_eX]

[DOI]

Sejong Oh

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Interconnect Criticality-Driven Delay Relaxation.

[BibT_eX]

[DOI]

David Eppstein

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Multi-layer floorplanning for reconfigurable designs.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Energy-aware co-processor selection for embedded processors on FPGAs.

[BibT_eX]

[DOI]

Amir Hossein Gholamipour

Proceedings of the 25th International Conference on Computer Design, 2007

Novel Multi-Layer floorplanning for Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Heterogeneous Floorplanner for FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Single-Event-Upset (SEU) Awareness in FPGA Routing.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

FABSYN: floorplan-aware bus architecture synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Statistical Analysis and Design of HARP FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Unified Theory of Timing Budget Management.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Physically-aware exploitation of component reuse in a partially reconfigurable architecture.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures.

[BibT_eX]

[DOI]

Simin Dai

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A scheduling algorithm for optimization and early planning in high-level synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Fast timing closure by interconnect criticality driven delay relaxation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

HARP: hard-wired routing pattern FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Floorplan-aware automated synthesis of bus-based communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Optimal integer delay-budget assignment on directed acyclic graphs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

A unified theory of timing budget management.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Incremental Timing Budget Management in Programmable Systems.

[BibT_eX]

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

Creating and exploiting flexibility in rectilinear Steiner trees.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On computation and resource management in an FPGA-based computation environment.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Customized regular channel design in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Optimal integer delay budgeting on directed acyclic graphs.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Instruction generation for hybrid reconfigurable systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Pattern routing: use and theory for increasing predictability andavoiding coupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Budget Management with Applications.

[BibT_eX]

[DOI]

Algorithmica, 2002

2001

Wirelength estimation based on rent exponents of partitioning and placement.

[BibT_eX]

[DOI]

Xiaojian Yang

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Design and analysis of physical design algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

An exact algorithm for coupling-free routing.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

A Super-Scheduler for Embedded Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Instruction Generation for Hybrid Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Creating and Exploiting Flexibility in Steiner Trees.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

RPack: routability-driven packing for cluster-based FPGAs.

[BibT_eX]

[DOI]

Seda Ogrenci Memik

Proceedings of ASP-DAC 2001, 2001

2000

Predictable Routing.

[BibT_eX]

[DOI]