El Mostapha Aboulhamid
Affiliations:- Université de Montréal, Canada
According to our database1,
El Mostapha Aboulhamid
authored at least 84 papers
between 1983 and 2019.
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Bibliography
2019
On the Fog-Cloud Cooperation: How Fog Computing can address latency concerns of IoT applications.
Proceedings of the Fourth International Conference on Fog and Mobile Edge Computing, 2019
2015
Int. J. Parallel Program., 2015
2013
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst., 2009
Introspection mechanisms for runtime verification in a system-level design environment.
Microelectron. J., 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
J. VLSI Signal Process., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
Generic discrete-continuous simulation model for accurate validation in heterogeneous systems design.
Microelectron. J., 2007
A high-level requirements engineering methodology for electronic system-level design.
Comput. Electr. Eng., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Introspection Mechanisms for Semi-Formal Verification in a System-Level Design Environment.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the Forum on specification and Design Languages, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Towards an Efficient Simulation of Multi-Language Descriptions of Heterogeneous Systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst., 2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
2004
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the Managing Next Generation Convergence Networks and Services, 2004
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors.
Proceedings of the 2004 Design, 2004
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation.
Proceedings of the 2004 Design, 2004
2003
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the Forum on specification and Design Languages, 2003
Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse.
Proceedings of the Patterns and Skeletons for Parallel and Distributed Computing, 2003
2002
Adder based residue to binary number converters for (2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1).
IEEE Trans. Signal Process., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
Comput. Commun., 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1999
Comput. Networks, 1999
A test case generation tool for conformance testing of SDL systems.
Proceedings of the SDL '99 The Next Millennium, 1999
Multithreading-based Coverification Technique of HW/SW Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem II.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
A Guided Incremental Test Case Generation Procedure for Conformance Testing for CEFSM Specified Protocols.
Proceedings of the Testing of Communicating Systems, IFIP TC6 11th International Workshop on Testing Communicating Systems (IWTCS), August 31, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Residue to Binary Number Converters for (2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1).
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1996
Lower bounds on the iteration time and the initiation interval of functional pipelining and loop folding.
Des. Autom. Embed. Syst., 1996
1994
1993
1992
Comput. Aided Des., 1992
1991
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991
1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
1984
IEEE Trans. Computers, 1984
1983