El-Bay Bourennane
Orcid: 0000-0002-4809-3002Affiliations:
- Bourgogne University, Dijon, France
According to our database1,
El-Bay Bourennane
authored at least 82 papers
between 1998 and 2024.
Collaborative distances:
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Bibliography
2024
HTC-retina: A hybrid retinal diseases classification model using transformer-Convolutional Neural Network from optical coherence tomography images.
Comput. Biol. Medicine, 2024
Proceedings of the 21st International Conference on Security and Cryptography, 2024
2023
Hardware implementation of a strong pseudorandom number generator based block-cipher system for color image encryption and decryption.
Int. J. Circuit Theory Appl., January, 2023
2022
High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding.
Integr., 2022
2021
A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM.
Int. J. Reconfigurable Comput., 2021
A dynamic multi-sink routing protocol for static and mobile self-organizing wireless networks: A routing protocol for Internet of Things.
Ad Hoc Networks, 2021
Proceedings of the IEEE Intl Conf on Dependable, 2021
2020
Int. J. Biom., 2020
Multimodal biometric recognition systems using deep learning based on the finger vein and finger knuckle print fusion.
IET Image Process., 2020
Future Internet, 2020
Comput. Commun., 2020
Proceedings of the 14th International Conference on Innovations in Information Technology, 2020
Artificial Intelligence and Cyber Security: Protecting and Maintaining Industry 4.0 Power Networks.
Proceedings of the third Conference on Informatics and Applied Mathematics, 2020
Multi-feature Counting of Dense Crowd Image Based on Multi-column Convolutional Neural Network.
Proceedings of the 5th International Conference on Computer and Communication Systems, 2020
2019
J. Real Time Image Process., 2019
Palmprint identification performance improvement via patch-based binarized statistical image features (Erratum).
J. Electronic Imaging, 2019
Palmprint identification performance improvement via patch-based binarized statistical image features.
J. Electronic Imaging, 2019
Adaptive neuro-fuzzy inference system based maximum power point tracking for stand-alone photovoltaic system.
Int. J. Model. Identif. Control., 2019
The analysis of unreliable M[X]/G/1 queuing system with loss, vacation and two delays of verification.
Commun. Stat. Simul. Comput., 2019
Proceedings of the 14th International Joint Conference on Computer Vision, 2019
Carbon monoxide detection: an IoT application used as a tool for civil protection services to save lives.
Proceedings of the 3rd International Conference on Future Networks and Distributed Systems, 2019
Proceedings of the 1st International Conference on Innovative Trends in Computer Science, 2019
2018
AODVCS, a new bio-inspired routing protocol based on cuckoo search algorithm for mobile ad hoc networks.
Wirel. Networks, 2018
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip.
J. Parallel Distributed Comput., 2018
A Graphical Modelling Editor for STARSoC Design Flow Tool Based on Model Driven Engineering Approach.
e Informatica Softw. Eng. J., 2018
Implementation of Real Time Reconfigurable Embedded Architecture for People Counting in a Crowd Area.
Proceedings of the Modelling and Implementation of Complex Systems, 2018
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018
An Efficient FPGA Implementation of Anisotropic Diffusion Function for Medical Images.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018
2017
Microprocess. Microsystems, 2017
Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interest.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
2016
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction.
J. Syst. Archit., 2016
Evol. Syst., 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
2015
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., 2015
Microprocess. Microsystems, 2015
Utilisation of the Array-OL specification language for self-generation of a memory controller especially for the H.264/AVC.
Int. J. Embed. Syst., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 27th International Conference on Microelectronics, 2015
2014
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014
Proceedings of the International Conference on Control, 2014
Proceedings of the International Conference on Control, 2014
2013
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems.
Microprocess. Microsystems, 2013
2012
A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile.
Des. Autom. Embed. Syst., 2012
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Model-Driven Approach for Automatic Dynamic Partially Reconfigurable IP Customization.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Microprocess. Microsystems, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
On the Use of Graph Transformation in the Modeling and Verification of Dynamic Behavior in UML Models.
J. Softw., 2010
A UML and Colored Petri Nets Integrated Modeling and Analysis Approach using Graph Transformation.
J. Object Technol., 2010
Towards Hardware implementation of video applications in new telecommunications devices
CoRR, 2010
Memory requirements and simulation platform for the implementation of the H.264 encoder modules.
Proceedings of the 2nd International Conference on Image Processing Theory Tools and Applications, 2010
2009
Modeling and Verification of Dynamic Behavior in UML Models: A Graph Transformation Approach.
Proceedings of the 18th International Conference on Software Engineering and Data Engineering (SEDE-2009), 2009
2008
SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication.
Int. J. Reconfigurable Comput., 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
A closed form solution for the blind separation of two sources from two sensors using second order statistics.
Proceedings of the 14th European Signal Processing Conference, 2006
2005
Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm.
EURASIP J. Adv. Signal Process., 2005
STARSoC : A C-based platform for rapid prototyping of embedded system.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2004
Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA.
Proceedings of the 2004 International Conference on Image Processing, 2004
Proceedings of the 2004 12th European Signal Processing Conference, 2004
2003
SVM approximation for real-time image segmentation by using an improved hyperrectangles-based method.
Real Time Imaging, 2003
Classification Boundary Approximation by Using Combination of Training Steps for Real-Time Image Segmentation.
Proceedings of the Machine Learning and Data Mining in Pattern Recognition, 2003
2002
Signal Process., 2002
Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs.
Proceedings of the IEEE International Conference on Acoustics, 2002
Real-time flaw detection on complex part: Study of SVM and hyperrectangle based method.
Proceedings of the IEEE International Conference on Acoustics, 2002
2001
Approches région et bayésienne pour la restauration ďimages dégradées par la turbulence atmosphérique.
Ann. des Télécommunications, 2001
1999
A principal component analysis based method for the Simulation of turbulence-degraded infrared image sequence.
Ann. des Télécommunications, 1999
1998
Real Time Imaging, 1998
Implementation of a Real Time Image Rotation using B-Spline Interpolation on FPGA's Board.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998
Proceedings of the 9th European Signal Processing Conference, 1998