Ekawat Homsirikamol
According to our database1,
Ekawat Homsirikamol
authored at least 22 papers
between 2010 and 2019.
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Bibliography
2019
A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography.
IACR Cryptol. ePrint Arch., 2019
2017
A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study.
Proceedings of the International Conference on Field Programmable Technology, 2017
2016
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the Progress in Cryptology - INDOCRYPT 2016, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
IACR Cryptol. ePrint Arch., 2014
Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl.
Microprocess. Microsystems, 2013
2012
IACR Cryptol. ePrint Arch., 2012
IACR Cryptol. ePrint Arch., 2012
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.
IACR Cryptol. ePrint Arch., 2012
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
2011
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011
2010
IACR Cryptol. ePrint Arch., 2010
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010