Ejaz Haq

According to our database1, Ejaz Haq authored at least 4 papers between 1993 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1993
1994
1995
1996
1997
1998
1999
2000
2001
0
1
2
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2001
JAZiO Signal-Switching Technology: A Low-Cost Digital I/O for High-Speed Applications.
IEEE Micro, 2001

1996
A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth.
IEEE J. Solid State Circuits, 1996

1994
16-Mb synchronous DRAM with 125-Mbyte/s data rate.
IEEE J. Solid State Circuits, April, 1994

1993
Variable V/sub CC/ design techniques for battery-operated DRAMs.
IEEE J. Solid State Circuits, April, 1993


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