Eitake Ibaragi

According to our database, Eitake Ibaragi authored at least 5 papers between 2000 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS.

Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu

IEEE J. Solid State Circuits, 2013

A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS.

Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2009

A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras.

Ronald Kapusta, Hiroto Shinozaki, Eitake Ibaragi, Kevin Ni, Richard Wang, Mark T. Sayuk, Larry Singer, Katsu Nakamura

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2001

A CMOS OTA free from second order effects with a high input resistance Gm control terminal.

Eitake Ibaragi, Soushirou Nishioka, Akira Hyogo, Keitaro Sekine

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A 1-MHz 7th-order continuous-time lowpass filter using very low distortion CMOS OTAs.

Eitake Ibaragi, Akira Hyogo, Keitaro Sekine

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000