Einar J. Aas

According to our database, Einar J. Aas authored at least 34 papers between 1975 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Design of embedded TCAM based longest prefix match search engine.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas

Microprocess. Microsystems, 2011

A programmable BIST with macro and micro codes for embedded SRAMs.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef

Proceedings of the 9th East-West Design & Test Symposium, 2011

An Enhanced Path Delay Fault Simulator for Combinational Circuits.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Experiments with ABIST test methodology applied to path delay fault testing.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Path-Delay Fault Testing in Embedded Content Addressable Memories.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Design of novel CAM core cell structures for an efficient implementation of low power BCAM system.

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.

Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas

J. Signal Process. Syst., 2008

Scan Test Response Compaction Combined with Diagnosis Capabilities.

Sverre Wichlund, Frank Berntsen, Einar J. Aas

J. Electron. Test., 2008

2007

Probabilistic gate-level power estimation using a novel waveform set method.

Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.

Sverre Wichlund, Frank Berntsen, Einar J. Aas

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor.

Sverre Wichlund, Einar J. Aas

Proceedings of the 15th Asian Test Symposium, 2006

2005

Remote Path Delay Fault Simulation.

Øystein Gjermundnes, Einar J. Aas

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

Storage requirement estimation for optimized design of data intensive applications.

Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas

ACM Trans. Design Autom. Electr. Syst., 2004

2003

Data dependency size estimation for use in memory optimization.

Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

On the Utilization of Java Technology in Embedded Systems.

Øyvind Strøm, Kjetil Svarstad, Einar J. Aas

Des. Autom. Embed. Syst., 2003

2001

Formal verification of digital circuits by 3-valued simulation.

Ayman M. Wahba, Einar J. Aas

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code.

Øyvind Strøm, Einar J. Aas

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.

Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas

Proceedings of the 38th Design Automation Conference, 2001

2000

Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences.

Einar J. Aas

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning.

Sverre Wichlund, Einar J. Aas

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering.

Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Storage requirement estimation for data intensive applications with partially fixed execution ordering.

Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Project based learning objectives and experiences in electronic education: a memory controller design experiment.

Einar J. Aas, Jukka Typpo

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs.

Øyvind Strøm, Audun Klauseie, Einar J. Aas

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1996

4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique.

Johnny Pihl, Einar J. Aas

Proceedings of the Fourth International Symposium on Signal Processing and Its Applications, 1996

Comparison of two architectures for implementation of the discrete cosine transform.

Ingil Sundsbo, G. Lokken Hansen, Einar J. Aas

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

1994

Quantifying Design Quality Through Design Experiments.

Einar J. Aas, Tore Steen, Karl Klingsheim

IEEE Des. Test Comput., 1994

1993

Verification and Diagnosis of Digital Systems by Termary Reasoning.

Ayman M. Wahba, Einar J. Aas

Proceedings of the Correct Hardware Design and Verification Methods, 1993

1991

Combined probabilistic testability calculation and compact test generation for PLAs.

Bjørg Reppen, Einar J. Aas

J. Electron. Test., 1991

Experiments with autonomous test of PLAs.

Einar J. Aas, Gunnar Nystu

Proceedings of the conference on European design automation, 1991

1990

State transition graph analysis as a key to BIST fault coverage.

Ove Brynestad, Einar J. Aas, Anne E. Vallestad

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1984

Test generation through logic programming.

Dag Svanæs, Einar J. Aas

Integr., 1984

1978

An integrated system for interactive editing of schematics, logic simulation and PCB layout design.

Hedayat Markus Bayegan, Einar J. Aas

Proceedings of the 15th Design Automation Conference, 1978

1975

Design automation in norway.

P. A. Arneberg, Einar J. Aas

Proceedings of the 12th Design Automation Conference, 1975