Eiki Imaizumi

According to our database, Eiki Imaizumi authored at least 5 papers between 1997 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver.

Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki

IEICE Trans. Electron., 2009

2007

1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver.

Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop.

Yasutoshi Aibara, Eiki Imaizumi, Hiroaki Takagishi, Tatsuji Matsuura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

1998

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter.

Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato

IEEE J. Solid State Circuits, 1998

1997

Error suppressing encode logic of FCDL in a 6-b flash A/D converter.

Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, Ryuushi Shimokawa

IEEE J. Solid State Circuits, 1997