Eiichi Sano

According to our database, Eiichi Sano authored at least 24 papers between 1988 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS.

Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2014

A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals.

Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

60-GHz, 9-µW wake-up receiver for short-range wireless communications.

Toshiki Wada, Masayuki Ikebe, Eiichi Sano

Proceedings of the ESSCIRC 2013, 2013

2012

A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals.

Kisu Kim, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network.

Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Column parallel single-slope ADC with time to digital converter for CMOS imager.

Muung Shin, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna.

Masayuki Ikebe, Daisuke Ueo, Kazuhiro Takahagi, Masaki Ohuno, Yusuke Takada, Eiichi Sano

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers.

Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007

Evaluation of Digitally Controlled PLL by Clock-Period Comparison.

Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano

IEICE Trans. Electron., 2007

Possibility of Terahertz Injection-Locked Oscillation in an InGaP/InGaAs/GaAs Two-Dimensional Plasmon-Resonant Photomixer.

Mitsuhiro Hanabe, Yahya Moubarak Meziani, Taiichi Otsuji, Eiichi Sano, Tanemasa Asano

IEICE Trans. Electron., 2007

2006

Terahertz Frequency Multiplier Operation of Two Dimensional Plasmon Resonant Photomixer.

Takuya Nishimura, Mitsuhiro Hanabe, Masaki Miyamoto, Taiichi Otsuji, Eiichi Sano

IEICE Trans. Electron., 2006

W-Band Active Integrated Antenna Oscillator Based on Full-Wave Design Methodology and 0.1-µm Gate InP-Based HEMTs.

Koji Inafune, Eiichi Sano, Hideaki Matsuzaki, Toshihiko Kosugi, Takatomo Enoki

IEICE Trans. Electron., 2006

Structure-Sensitive Design for Wider Tunable Operation of Terahertz Plasmon-Resonant Photomixer.

Mitsuhiro Hanabe, Takuya Nishimura, Masaki Miyamoto, Taiichi Otsuji, Eiichi Sano

IEICE Trans. Electron., 2006

A chaotic wireless communication system based on collective synchronization among wireless nodes.

Eiichi Sano

IEICE Electron. Express, 2006

2004

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.

Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi

IEEE J. Solid State Circuits, 2004

RF CMOS inductor shielded by a high-impedance surface.

Eiichi Sano, Koji Inafune, Masamichi Akazawa

IEICE Electron. Express, 2004

2002

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors.

Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki

IEEE J. Solid State Circuits, 2002

2001

An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode.

Kimikazu Sano, Koichi Murata, Taiichi Otsuji, Tomoyuki Akeyoshi, Naofumi Shimizu, Eiichi Sano

IEEE J. Solid State Circuits, 2001

High-speed lightwave communication ICs based on III-V compound semiconductors.

Eiichi Sano

IEEE Commun. Mag., 2001

1999

Circuit design technologies for high-speed lightwave communications beyond 40 Gbit/s.

Shunji Kimura, Taiichi Otsuji, Hiroyuki Kikuchi, Koichi Murata, Eiichi Sano

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997

A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs.

Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano

IEEE J. Solid State Circuits, 1997

40-Gb/s ICs for future lightwave communications systems.

Taiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda

IEEE J. Solid State Circuits, 1997

1995

A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET.

Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Minoru Togashi, Masao Suzuki

IEEE J. Solid State Circuits, October, 1995

1988

Performance limits of mixed analog/digital circuits with scaled MOSFETs.

Eiichi Sano, Tsuneo Tsukahara, Atsushi Iwata

IEEE J. Solid State Circuits, August, 1988