Ehsan K. Ardestani

Orcid: 0000-0003-1267-6887

According to our database1, Ehsan K. Ardestani authored at least 19 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2023
MTrainS: Improving DLRM training efficiency using heterogeneous memories.
CoRR, 2023


2022

Supporting Massive DLRM Inference through Software Defined Memory.
Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022

Building a Performance Model for Deep Learning Recommendation Model Training on GPUs.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

2021
Supporting Massive DLRM Inference Through Software Defined Memory.
CoRR, 2021

High-performance, Distributed Training of Large-scale Deep Learning Recommendation Models.
CoRR, 2021

2018
GPU NTC Process Variation Compensation With Voltage Stacking.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2016
Managing Mismatches in Voltage Stacking with CoreUnfolding.
ACM Trans. Archit. Code Optim., 2016

2014
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An energy efficient GPGPU memory hierarchy with tiny incoherent caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

ESESC: A fast multicore simulator using Time-Based Sampling.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

ESESC: A fast performance, power, and temperature multicore simulator.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

2012
Thermal-aware sampling in architectural simulation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

CHAOS: Composable Highly Accurate OS-based power models.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2010
Characterizing processor thermal behavior.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Using randomization to cope with circuit uncertainty.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008


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