Efstathios D. Kyriakis-Bitzaros

According to our database1, Efstathios D. Kyriakis-Bitzaros authored at least 18 papers between 1991 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Performance of MicroMegas Electronics in a High-Radiation Environment.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2020
Validation of the Production-Phase Level-1 Data Driver Cards for the Readout and Trigger System of the ATLAS New Small Wheel Detector.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2018
Design and implementation of a re-configurable embedded system for capacitive sensor array interface.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
Testing the Level-1 Data Driver Card for the New Small Wheel of the ATLAS detector.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2011
A Reconfigurable Multichannel Capacitive Sensor Array Interface.
IEEE Trans. Instrum. Meas., 2011

2009
Conceptual Design of a Wireless Strain Monitoring System for Space Applications.
Proceedings of the Mobile Lightweight Wireless Systems, 2009

2007
VCSEL device modeling and parameter extraction technique.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2000
Estimation of signal transition activity in FIR filters implementedby a MAC architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1.7 GHz bipolar optoelectronic receiver using conventional 0.8 μm BiCMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays.
J. VLSI Signal Process., 1999

A Charge Recycling Technique for the Design of Low Power CMOS Clock Drivers.
J. Circuits Syst. Comput., 1999

Estimation of the transition activity in MAC architectures implementing FIR filters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Accurate calculation of bit-level transition activity using word-level statistics and entropy function.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1996
Transformation of Nested Loops into Uniform Recurrences and their Mapping to Regular Processor Arrays.
J. Circuits Syst. Comput., 1996

1993
Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992
An Efficient Decompostion Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays.
J. Parallel Distributed Comput., 1992

A Systematic Partitioning Method for Designing Fixed-Size Processor Arrays.
J. Circuits Syst. Comput., 1992

1991
A real time speech decoder using instantaneous frequency and energy.
Proceedings of the Second European Conference on Speech Communication and Technology, 1991


  Loading...