Edwin Rijpkema

According to our database, Edwin Rijpkema authored at least 12 papers between 1997 and 2005.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2005

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.

Andrei Radulescu, John Dielissen, Santiago González Pestana, Om Prakash Gangwal, Edwin Rijpkema, Paul Wielage, Kees Goossens

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.

Kees Goossens, John Dielissen, Om Prakash Gangwal, Santiago González Pestana, Andrei Radulescu, Edwin Rijpkema

Proceedings of the 2005 Design, 2005

Deadlock Prevention in the Æthereal Protocol.

Biniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.

Andrei Radulescu, John Dielissen, Kees Goossens, Edwin Rijpkema, Paul Wielage

Proceedings of the 2004 Design, 2004

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.

Santiago González Pestana, Edwin Rijpkema, Andrei Radulescu, Kees Goossens, Om Prakash Gangwal

Proceedings of the 2004 Design, 2004

2003

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.

Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander

Proceedings of the 2003 Design, 2003

Guaranteeing the Quality of Services in Networks on Chip.

Kees Goossens, John Dielissen, Jef L. van Meerbergen, Peter Poplavko, Andrei Radulescu, Edwin Rijpkema, Erwin Waterlander, Paul Wielage

Proceedings of the Networks on Chip, 2003

2002

Translating Imperative Affine Nested Loop Programs into Process Networks.

Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis

Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

2000

Deriving Process Networks from Nested Loop Algorithms.

Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis

Parallel Process. Lett., 2000

Compaan: deriving process networks from Matlab for embedded signal processing architectures.

Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

High Level Modeling for Parallel Executions of Nested Loop Algorithms.

Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1997

A strategy for determining a Jacobi specific dataflow processor.

Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997