Edward S. Davidson

According to our database, Edward S. Davidson authored at least 97 papers between 1968 and 2014.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2014

Author retrospective for optimum modulo schedules for minimum register requirements.

Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham

Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2008

A freespace crossbar for multi-core processors.

Michel N. Victor, Aris K. Silzars, Edward S. Davidson

Proceedings of the 22nd Annual International Conference on Supercomputing, 2008

2004

A Prefetch Taxonomy.

Viji Srinivasan, Edward S. Davidson, Gary S. Tyson

IEEE Trans. Computers, 2004

Probabilistic Predicate-Aware Modulo Scheduling.

Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson

Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

2003

Call graph prefetching for database applications.

Murali Annavaram, Jignesh M. Patel, Edward S. Davidson

ACM Trans. Comput. Syst., 2003

Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints.

Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee

Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002

Boosting trace cache performance with nonhead miss speculation.

Stevan A. Vlaovic, Edward S. Davidson

Proceedings of the 16th international conference on Supercomputing, 2002

TAXI: Trace Analysis for X86 Interpretation.

Stevan A. Vlaovic, Edward S. Davidson

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Evaluating the Use of Register Queues in Software Pipelined Loops.

G. X. Tyson, M. Smelyanskyi, Edward S. Davidson

IEEE Trans. Computers, 2001

Data prefetching by dependence graph precomputation.

Murali Annavaram, Jignesh M. Patel, Edward S. Davidson

Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme.

Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Branch History Guided Instruction Prefetching.

Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000

Improving BTB performance in the presence of DLLs.

Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Instruction overhead and data locality effects in superscalar processors.

Murali Annavaram, Gary S. Tyson, Edward S. Davidson

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining.

Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson

Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999

Active Management of Data Caches by Exploiting Reuse Information.

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson

IEEE Trans. Computers, 1999

Introduction to "The ENIAC".

Arthur W. Burks, Edward S. Davidson

Proc. IEEE, 1999

Dual-Issue Scheduling with Spills for Binary Trees.

Waleed Meleis, Edward S. Davidson

Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms, 1999

1998

Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000.

Gheith A. Abandah, Edward S. Davidson

IEEE Trans. Parallel Distributed Syst., 1998

mlcache: A Flexible Multi-Lateral Cache Simulator.

Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson

Proceedings of the MASCOTS 1998, 1998

Retrospective: The Cedar System.

Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

The Cedar System and an Initial Performance Study.

David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance.

Gheith A. Abandah, Edward S. Davidson

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

Configuration Independent Analysis for Characterizing Shared-Memory Applications.

Gheith A. Abandah, Edward S. Davidson

Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Utilizing Reuse Information in Data Cache Management.

Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens

Proceedings of the 12th international conference on Supercomputing, 1998

Evaluating the performance of active cache management schemes.

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Origin 2000 Design Enhancements for Communication Intensive Applications.

Gheith A. Abandah, Edward S. Davidson

Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997

Efficient Formulation for Optimal Modulo Schedulers.

Alexandre E. Eichenberger, Edward S. Davidson

Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), 1997

On High-Bandwidth Data Cache Design for Multi-Issue Processors.

Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

On Effective Data Supply For Multi-Issue Processors.

Jude A. Rivers, Edward S. Tam, Edward S. Davidson

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Performance Issues in Integrating Temporality-Based Caching with Prefetching.

Jude A. Rivers, Edward S. Davidson

Perform. Evaluation, 1996

Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling.

Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham

Int. J. Parallel Program., 1996

A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints.

Alexandre E. Eichenberger, Edward S. Davidson

Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), 1996

Modeling the Communication Performance of the IBM SP2.

Gheith A. Abandah, Edward S. Davidson

Proceedings of IPPS '96, 1996

Profile Driven Weighted Decomposition.

Karen A. Tomko, Edward S. Davidson

Proceedings of the 10th international conference on Supercomputing, 1996

Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design.

Jude A. Rivers, Edward S. Davidson

Proceedings of the 1996 International Conference on Parallel Processing, 1996

1995

Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.

Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Stage scheduling: a technique to reduce the register requirements of a modulo schedule.

Alexandre E. Eichenberger, Edward S. Davidson

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Register allocation for predicated code.

Alexandre E. Eichenberger, Edward S. Davidson

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Optimum Modulo Schedules for Minimum Register Requirements.

Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham

Proceedings of the 9th international conference on Supercomputing, 1995

The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.

John-David Wellman, Edward S. Davidson

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

Minimum register requirements for a modulo schedule.

Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Optimal local register allocation for a multiple-issue machine.

Waleed Meleis, Edward S. Davidson

Proceedings of the 8th international conference on Supercomputing, 1994

Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments.

Eric L. Boyd, Edward S. Davidson

Proceedings of the 8th international conference on Supercomputing, 1994

A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1.

Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson

Proceedings of the 1994 International Conference on Parallel Processing, 1994

Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs.

Tien-Pao Shih, Edward S. Davidson

Proceedings of the Proceedings 1994 International Conference on Parallel and Distributed Systems, 1994

1993

Synchronization of pipelines.

Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Approaching a machine-application bound in delivered performance on scientific code.

William H. Mangione-Smith, Tien-Pao Shih, Santosh G. Abraham, Edward S. Davidson

Proc. IEEE, 1993

The Cedar System and an Initial Performance Study.

David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240.

Eric L. Boyd, Edward S. Davidson

Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver.

Daniel Windheiser, Eric L. Boyd, Eric Hao, Santosh G. Abraham, Edward S. Davidson

Proceedings of the Seventh International Parallel Processing Symposium, 1993

Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads.

Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson

Proceedings of the 7th international conference on Supercomputing, 1993

1992

Register requirements of pipelined processors.

William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson

Proceedings of the 6th international conference on Supercomputing, 1992

Using constraint geometry to determine maximum rate pipeline clocking.

Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1.

William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson

Computer, 1991

An integrated approach to developing manufacturing control software.

Jarir K. Chaar, Richard A. Volz, Edward S. Davidson

Proceedings of the 1991 IEEE International Conference on Robotics and Automation, 1991

The Organization of the Cedar System.

Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter

Proceedings of the International Conference on Parallel Processing, 1991

Optimal Clocking of Circular Pipelines.

Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Vector Register Design for Polycyclic Vector Scheduling.

William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson

Proceedings of the ASPLOS-IV Proceedings, 1991

1990

Cyclic job shop scheduling using reservation tables.

Jarir K. Chaar, Edward S. Davidson

Proceedings of the 1990 IEEE International Conference on Robotics and Automation, 1990

1988

Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations.

Timothy A. Davis, Edward S. Davidson

IEEE Trans. Computers, 1988

Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers.

J. H. Tang, Edward S. Davidson, J. Tong

Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

Analysis of Memory Referencing Behavior For Design of Local Memories.

Geoffrey D. McNiven, Edward S. Davidson

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels.

J. H. Tang, Edward S. Davidson

Proceedings of the 2nd international conference on Supercomputing, 1988

1987

Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance.

Philip G. Emma, Edward S. Davidson

IEEE Trans. Computers, 1987

PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations.

Timothy A. Davis, Edward S. Davidson

Proceedings of the International Conference on Parallel Processing, 1987

1986

Highly Concurrent Scalar Processing.

Peter Y.-T. Hsu, Edward S. Davidson

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

A Communication Model for Optimizing Hierarchical Multiprocessor Systems.

Santosh G. Abraham, Edward S. Davidson

Proceedings of the International Conference on Parallel Processing, 1986

Features of the Structured Memory Access (SMA) Architecture.

Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson

Proceedings of the Spring COMPCON'86, 1986

A Broader Range of Possible Answers to the Issues Raised by RISC.

Edward S. Davidson

Proceedings of the Spring COMPCON'86, 1986

1985

An Efficient LISP-Execution Architecture with a New Representation for List Structures.

Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel

Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology.

Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham

Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

A custom-designed integrated circuit for the realization of residue number digital filters.

W. K. Jenkins, Edward S. Davidson, D. F. Paul

Proceedings of the IEEE International Conference on Acoustics, 1985

1984

Design of Instruction Set Architectures for Support of High-Level Languages .

Pradip Bose, Edward S. Davidson

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1983

Shared Cache for Multiple-Stream Computer Systems.

Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson

IEEE Trans. Computers, 1983

Performance of Shared Cache for Parallel-Pipelined Computer Systems

Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson

Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

Structured Memory Access Architecture.

Andrew R. Pleszkun, Edward S. Davidson

Proceedings of the International Conference on Parallel Processing, 1983

1982

Memory Interference in Synchronous Multiprocessor Systems.

David W. L. Yen, Janak H. Patel, Edward S. Davidson

IEEE Trans. Computers, 1982

Evaluating database management systems.

Edward S. Davidson

Proceedings of the American Federation of Information Processing Societies: 1982 National Computer Conference, 1982

1981

DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer.

Robert L. Budzinski, Edward S. Davidson, Wataru Mayeda, Harold S. Stone

IEEE Trans. Software Eng., 1981

A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms.

Robert L. Budzinski, Edward S. Davidson

IEEE Trans. Software Eng., 1981

1980

Computer System Design Using a Hierarchical Approach to Performance Evaluation.

B. Kumar, Edward S. Davidson

Commun. ACM, 1980

A Multiple Stream Microprocessor Prototype System: AMP-1.

Edward S. Davidson

Proceedings of the 7th Annual Symposium on Computer Architecture, 1980

1979

Special Feature: Developing a Multiple-Instruction-Stream Single-Chip Processor.

William Joseph Kaminsky Jr., Edward S. Davidson

Computer, 1979

1978

Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation.

B. Kumar, Edward S. Davidson

Commun. ACM, 1978

1977

Organization of Semiconductor Memories for Parallel-Pipelined Processors.

Faye A. Briggs, Edward S. Davidson

IEEE Trans. Computers, 1977

Information Content of CPU Memory Referencing Behavior.

Dan W. Hammerstrom, Edward S. Davidson

Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

1976

Improving the Throughput of a Pipeline by Insertion of Delays.

Janak H. Patel, Edward S. Davidson

Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976

1974

Redundancy Testing in Combinational Networks.

Hsien-Hsin S. Lee, Edward S. Davidson

IEEE Trans. Computers, 1974

A multiminiprocessor system implemented through pipelining.

Leonard E. Shar, Edward S. Davidson

Computer, 1974

Optimal Searching Algorithms for Parallel Pipelined Computers.

Daniel L. Weller, Edward S. Davidson

Proceedings of the Parallel Processing, Proceedings of the Sagamore Computer Conference, 1974

1972

Comments on "A Minimization Technique for TANT Networks".

Hsiao-Peng Lee, Edward S. Davidson

IEEE Trans. Computers, 1972

A Transform for NAND Network Design.

Hsiao-Peng Lee, Edward S. Davidson

IEEE Trans. Computers, 1972

1969

Authors' Reply⁴.

Edward S. Davidson, Gernot Metze

IEEE Trans. Computers, 1969

An Algorithm for NAND Decomposition Under Network Constraints.

Edward S. Davidson

IEEE Trans. Computers, 1969

1968

An Algorithm for Nand Decomposition of Combinational Switching Functions

Edward S. Davidson

PhD thesis, 1968

Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic".

Edward S. Davidson, Gernot Metze

IEEE Trans. Computers, 1968