Edward Jongyoon Choi
Orcid: 0000-0002-3809-9734
According to our database1,
Edward Jongyoon Choi
authored at least 6 papers
between 2022 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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2023
2024
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Bibliography
2024
Skew-CIM: Process-Variation-Resilient and Energy-Efficient Computation-in-Memory Design Technique With Skewed Weights.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm<sup>2</sup>.
Proceedings of the 21st International SoC Design Conference, 2024
2023
A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022