Edward Flanigan
According to our database1,
Edward Flanigan
authored at least 9 papers
between 2006 and 2010.
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Bibliography
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
2008
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model.
Proceedings of the 2008 IEEE International Test Conference, 2008
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006