Edward Flanigan

According to our database1, Edward Flanigan authored at least 9 papers between 2006 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Identification of Delay Measurable PDFs Using Linear Dependency Relationships.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2008
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model.
Proceedings of the 2008 IEEE International Test Conference, 2008

Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Novel Test Generation Methodology for Adaptive Diagnosis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Enhanced Identification of Strong Robustly Testable Paths.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
An Improved Method for Identifying Linear Dependencies in Path Delay Faults.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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