Eduardo Augusto Bezerra

Orcid: 0000-0002-2191-6064

Affiliations:
  • Federal University of Santa Catarina, Florianópolis, Brazil


According to our database1, Eduardo Augusto Bezerra authored at least 69 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FloripaSat-2: An Open-Source Platform for CubeSats.
IEEE Embed. Syst. Lett., March, 2024

Hardware-in-the-Loop Simulation of an On-Board Energy-Driven Scheduling Algorithm for CubeSats.
IEEE Embed. Syst. Lett., March, 2024

A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA.
Microprocess. Microsystems, 2024

Benders decomposition for the energy aware task scheduling of constellations of nanosatellites.
Comput. Oper. Res., 2024

TinyML Applied in Hyperspectral Image Classification on COTS Microcontroller.
Proceedings of the XIV Brazilian Symposium on Computing Systems Engineering, 2024

A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
MPPT aware task scheduling for nanosatellites using MIP-based ReLU proxy models.
Expert Syst. Appl., December, 2023

Improving energy aware nanosatellite task scheduling by a branch-cut-and-price algorithm.
Comput. Oper. Res., October, 2023

Explainable column-generation-based genetic algorithm for knapsack-like energy aware nanosatellite task scheduling.
Appl. Soft Comput., September, 2023

On-board energy scheduling optimization algorithm for nanosatellites.
Int. J. Circuit Theory Appl., August, 2023

RNS processor using moduli sets of the form 2<sup><i>n</i></sup>±1.
Int. J. Circuit Theory Appl., July, 2023

Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA.
IEEE Embed. Syst. Lett., June, 2023

A Graph Neural Network Approach to Nanosatellite Task Scheduling: Insights into Learning Mixed-Integer Models.
CoRR, 2023

Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism.
IEEE Access, 2023

2022
An Energy-Aware Task Scheduling for Quality-of-Service Assurance in Constellations of Nanosatellites.
Sensors, 2022

Multi-sector discrete-time channel model for data link layer evaluation of CubeSat communications.
Expert Syst. Appl., 2022

A branch-and-price algorithm for nanosatellite task scheduling to improve mission quality-of-service.
Eur. J. Oper. Res., 2022

A continuous-time formulation for optimal task scheduling and quality-of-service assurance in nanosatellites.
Comput. Oper. Res., 2022

Exploring Data Preprocessing and Machine Learning Methods for Forecasting Worldwide Fertilizers Consumption.
Proceedings of the International Joint Conference on Neural Networks, 2022

2021
Universal Verification Platform and Star Simulator for Fast Star Tracker Design.
Sensors, 2021

Static Attitude Determination Using Convolutional Neural Networks.
Sensors, 2021

MPI hardware framework for many-core based embedded systems.
Int. J. Sens. Networks, 2021

A nanosatellite task scheduling framework to improve mission value using fuzzy constraints.
Expert Syst. Appl., 2021

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Technology Impact on Neutron-Induced Effects in SDRAMs: A Comparative Study.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020
Finite-State Markov Chains Channel Model for CubeSats Communication Uplink.
IEEE Trans. Aerosp. Electron. Syst., 2020

Centroid determination hardware algorithm for star trackers.
Int. J. Sens. Networks, 2020

Nanosatellite electrical power system architectures: Models, simulations, and tests.
Int. J. Circuit Theory Appl., 2020

2019
Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design.
Sensors, 2019

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.
J. Electron. Test., 2019

A Fault-Tolerant Reconfigurable Platform for Communication Modules of Satellites.
Proceedings of the IEEE Latin American Test Symposium, 2019

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router.
Proceedings of the IEEE Latin American Test Symposium, 2019

2018
Agent-Based Simulation of Learning Dissemination in a Project-Based Learning Context Considering the Human Aspects.
IEEE Trans. Educ., 2018

A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs.
Microelectron. Reliab., 2018

An efficient EDAC approach for handling multiple bit upsets in memory array.
Microelectron. Reliab., 2018

On the students' perceptions of the knowledge formation when submitted to a Project-Based Learning environment using web applications.
Comput. Educ., 2018

Processor checkpoint recovery for transient faults in critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Processor core profiling for SEU effect analysis.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Analysis of LEON3 systems integration for a Network-on-Chip.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
A Digital Implementation of Eddystone Standard Using IBM 180nm Cell Library.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017


2015
Experimental analysis of solar energy harvesting circuits efficiency for low power applications.
Comput. Electr. Eng., 2015

FPGA redundancy recovery based on partial bitstreams for multiple partitions.
Proceedings of the 16th Latin-American Test Symposium, 2015

A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A reconfigurable hardware platform for power converter control systems.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014
Low cost fault detector guided by permanent faults at the end of FPGAs life cycle.
Proceedings of the 15th Latin American Test Workshop, 2014

Hardware implementation of two key equation solvers for Reed-Solomon decoding.
Proceedings of the IEEE Latin-America Conference on Communications, 2014

2013
Automatic property generation for formal verification applied to HDL-based design of an on-board computer for space applications.
Proceedings of the 14th Latin American Test Workshop, 2013

2012
Towards a model to explore business opportunities in trail-aware environments.
Proceedings of the Brazilian Symposium on Multimedia and the Web, 2012

Non-intrusive fault tolerance in soft processors through circuit duplication.
Proceedings of the 13th Latin American Test Workshop, 2012

2011
eCloudRFID - A mobile software framework architecture for pervasive RFID-based applications.
J. Netw. Comput. Appl., 2011

2010
Automating the enterprise business processes in a supply chain environment through RFID services based on CEP technology.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

An adaptive communications module for on-board computers of satellites.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
An Adaptative Framework Architecture for RFID Applications.
Proceedings of the 33rd Annual IEEE Software Engineering Workshop, 2009

Using CloudRFID Middleware for Fuel Supply Control of Vehicles Fleets.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2009

2008
A Passive 915 MHz UHF RFID Tag.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
A Flexible Design Flow for a Low Power RFID Tag.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A 915 MHz UHF low power RFID tag.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
Observing SRAM-based FPGA Robustness in EMI-exposed Environments.
Proceedings of the 7th Latin American Test Workshop, 2006

2004
Towards service and user discovery on wireless networks.
Proceedings of the Second International Workshop on Mobility Management & Wireless Access Protocols, 2004

Mutation-Like Oriented Diversity for Dependability Improvement: A Distributed System Case Study.
Proceedings of the Computer and Information Sciences, 2004

2001
Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study.
J. Electron. Test., 2001

Using the CAN Protocol and Reconfigurable Computing Technology for Web-Based Smart House Auto.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

2000
A guide to migrating from microprocessor to FPGA coping with the support tool limitations.
Microprocess. Microsystems, 2000

Merging BIST and Configurable Computing Technology to Improve Availability in Space Applications.
Proceedings of the 1st Latin American Test Workshop, 2000

1998
Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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