Eduardo A. C. da Costa
Orcid: 0000-0003-0521-5898Affiliations:
- Federal University of Pelotas, Brazil
According to our database1,
Eduardo A. C. da Costa
authored at least 159 papers
between 2000 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025
2024
Exploring Discrete Haar Wavelet and Cosine Transforms for Accuracy-and Energy-Quality VLSI Watermarking Systems Design.
Circuits Syst. Signal Process., December, 2024
VLSI Architecture for Energy-Efficient and Accurate Pre-Processing Pan-Tompkins Design.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
AxRSU-2<sup>m</sup>: Higher-Order m-Bit Approximate Encoders for Radix-2<sup>m</sup> Squarer Units.
Circuits Syst. Signal Process., June, 2024
VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI Design.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024
Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse Injection.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Energy-Efficient VLSI Squarer Unit with Optimized Radix-2<sup>m</sup> Multiplication Logic.
Circuits Syst. Signal Process., February, 2023
ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
IEEE Trans. Very Large Scale Integr. Syst., 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
Accuracy-, Delay- and Area-Driven Evaluation of Lower-Part Approximate Parallel Prefix Adder.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
An Optimized VLSI Exponential Unit Design Exploring Efficient Arithmetic Operation Strategies.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
An Ultra Low-Energy VLSI Approximate Discrete Haar Wavelet Transform for ECG Data Compression.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2022
Bridging the Gap Between Voltage Over-Scaling and Joint Hardware Accelerator-Algorithm Closed-Loop.
IEEE Trans. Circuits Syst. Video Technol., 2022
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers.
IEEE Trans. Computers, 2022
The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures.
Circuits Syst. Signal Process., 2022
Improved Approximate Multipliers for Single-Precision Floating-Point Hardware Design.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Discrete Haar Wavelet Transform Hardware Design for Energy-Efficient Image Watermarking.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An Energy-Efficient Haar Wavelet Transform Architecture for Respiratory Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Biomed. Circuits Syst., 2021
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors.
IET Comput. Digit. Tech., 2021
Exploring NLMS-Based Adaptive Filter Hardware Architectures for Eliminating Power Line Interference in EEG Signals.
Circuits Syst. Signal Process., 2021
Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Boosting the Efficiency of the Harmonics Elimination VLSI Architecture by Arithmetic Approximations.
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders.
IEEE Trans. Circuits Syst. Video Technol., 2020
Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding.
J. Real Time Image Process., 2020
An Energy-Efficient and Approximate Accelerator Design for Real-Time Canny Edge Detection.
Circuits Syst. Signal Process., 2020
Power-Efficient Approximate Newton-Raphson Integer Divider Applied to NLMS Adaptive Filter for High-Quality Interference Cancelling.
Circuits Syst. Signal Process., 2020
Improving the Partial Product Tree Compression on Signed Radix-2<sup>m</sup> Parallel Multipliers.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Optimizing the Montgomery Modular Multiplier for a Power- and Area-Efficient Hardware Architecture.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Combining m=2 Multipliers and Adder Compressors for Power Efficient Radix-4 Butterfly.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Circuits Syst. Signal Process., 2019
Maximizing the Power-Efficiency of the Approximate Pruned Modified Rounded DCT Exploiting Approximate Adder Compressors.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Exploring Architectural Solutions for an Energy-Efficient Kalman Filter Gain Realization.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 2018 New Generation of CAS, 2018
Power System Frequency Estimation U Sing the Kernel Least Mean Square Algorithm and the Clarke Transform.
Proceedings of the 2018 New Generation of CAS, 2018
Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A power-predictive environment for fast and power-aware ASIC-based FIR filter design.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017
Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Pruning and approximation of coefficients for power-efficient 2-D Discrete Tchebichef Transform.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Exploring the combination of number of bits and number of iterations for a power-efficient fixed-point CORDIC implementation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Exploring the use of parallel prefix adder topologies into approximate adder circuits.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Using adder compressors for power-efficient 2-D approximate Discrete Tchebichef Transform.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Exploiting architectural solutions for IIR filter architecture with truncation error feedback.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Exploiting approximate adder circuits for power-efficient Gaussian and Gradient filters for Canny edge detector algorithm.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
A power-efficient imprecise radix-4 multiplier applied to high resolution audio processing.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Power efficient 2-D rounded cosine transform with adder compressors for image compression.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Energy-efficient Gaussian filter for image processing using approximate adder circuits.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Floating-point adaptive filter architectures for the cancelling of harmonics power line interference.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Combination of radix-2<sup>m</sup> multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancelling.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Fixed-point adaptive filter architecture for the harmonics power line interference cancelling.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Design of an efficient FPGA-based interference canceller structure using NLMS adaptive algorithm.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Exploration of tradeoffs in the design of integer cosine transforms for image compression.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications.
Integr., 2012
Efficient area and power multiplication part of FFT based on twiddle factor decomposition.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Finding the optimal tradeoff between area and delay in multiple constant multiplications.
Microprocess. Microsystems, 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Exploring the use of heuristic-based algorithms for the ordering and partitioning of coefficients for power efficient fir filters realization.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Design of low-power multiple constant multiplications using low-complexity minimum depth operations.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Optimization of gate-level area in high throughput Multiple Constant Multiplications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Efficient Dedicated Multiplication Blocks for 2's Complement Radix-2m Array Multipliers.
J. Comput., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
2007
A new array architecture for signed multiplication using Gray encoded radix-2<sup>m</sup> operands.
Integr., 2007
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Minimum number of operations under a general number representation for digital filter synthesis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.
Proceedings of the 43rd Design Automation Conference, 2006
2005
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Design of a radix-2<sup>m</sup> hybrid array multiplier using carry save adder format.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
2000
Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000