Eduard Babayan

According to our database1, Eduard Babayan authored at least 7 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

1.9 GHz 1.05V 16-bit RISC core for high density and low power operation in 28nm technology.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Synopsys' Educational Generic Memory Compiler.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2012
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Digital circuits verification with consideration of destabilizing factors.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

2010
Stable current and voltage generation under process variation.
Proceedings of the 2010 East-West Design & Test Symposium, 2010


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