Edoardo Fusella

According to our database, Edoardo Fusella authored at least 21 papers between 2013 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2019

Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.

Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha

ACM J. Emerg. Technol. Comput. Syst., 2019

2018

Lattice-Based Turn Model for Adaptive Routing.

Edoardo Fusella, Alessandro Cilardo

IEEE Trans. Parallel Distributed Syst., 2018

Exploring manycore architectures for next-generation HPC systems through the MANGO approach.

José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni

Microprocess. Microsystems, 2018

Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping.

Edoardo Fusella, Alessandro Cilardo

ACM J. Emerg. Technol. Comput. Syst., 2018

Improving Deep Learning with a customizable GPU-like FPGA-based accelerator.

Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Understanding turn models for adaptive routing: The modular approach.

Edoardo Fusella, Alessandro Cilardo

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

H²ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology.

Edoardo Fusella, Alessandro Cilardo

IEEE Trans. Very Large Scale Integr. Syst., 2017

Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby.

Edoardo Fusella, José Flich, Alessandro Cilardo

IEEE Trans. Parallel Distributed Syst., 2017

Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.

José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell

Proceedings of the Parallel Computing is Everywhere, 2017

A Deterministic Approach to Improve Inter-Domain Parallelism of Clustered MPSoC Interconnects.

Edoardo Fusella

Proceedings of the 31st International Conference on Advanced Information Networking and Applications Workshops, 2017

2016

Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip.

Edoardo Fusella, Alessandro Cilardo

ACM Trans. Embed. Comput. Syst., 2016

Minimizing power loss in optical networks-on-chip through application-specific mapping.

Edoardo Fusella, Alessandro Cilardo

Microprocess. Microsystems, 2016

Design automation for application-specific on-chip interconnects: A survey.

Alessandro Cilardo, Edoardo Fusella

Integr., 2016

PhoNoCMap: An application mapping tool for photonic networks-on-chip.

Edoardo Fusella, Alessandro Cilardo

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

ACM Trans. Embed. Comput. Syst., 2015

Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip.

Edoardo Fusella, Alessandro Cilardo

Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs.

Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo

Proceedings of the 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, 2015

Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip.

Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Automated design space exploration for FPGA-based heterogeneous interconnects.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca

Des. Autom. Embed. Syst., 2014

Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Automated synthesis of FPGA-based heterogeneous interconnect topologies.

Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013