Edna Barros

Orcid: 0000-0001-6479-3052

Affiliations:
  • Federal University of Pernambuco, Computer Science Department


According to our database1, Edna Barros authored at least 98 papers between 1993 and 2024.

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Bibliography

2024
Planning the path with Reinforcement Learning: Optimal Robot Motion Planning in RoboCup Small Size League Environments.
CoRR, 2024

2023
Uma Abordagem para Ensino-Aprendizado de Projetos de Sistemas Computacionais com Utilização do Simulador CompSim com Suporte à Arquitetura RISC-V.
Revista Brasileira de Informática na Educ., 2023

RobôCIn Small Size League Extended Team Description Paper for RoboCup 2023.
CoRR, 2023

A Soil pH Sensor and a Based on Time-Series Prediction IoT System for Agriculture.
Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023

Improving Inertial Odometry Through Particle Swarm Optimization in the RoboCup Small Size League.
Proceedings of the RoboCup 2023: Robot World Cup XXVI [Bordeaux, France, 4-10 July, 2023]., 2023

RobôCIn SSL-Unification: A Modular Software Architecture for Dynamic Multi-robot Systems.
Proceedings of the RoboCup 2023: Robot World Cup XXVI [Bordeaux, France, 4-10 July, 2023]., 2023

Dataset and Baseline Experiments for Self-Localization and Tracking in the RoboCup Small Size League.
Proceedings of the Latin American Robotics Symposium, 2023

2022
FPGA-Based Pedestrian Detection for Collision Prediction System.
Sensors, 2022

Web Soccer Monitor: An Open-Source 2D Soccer Simulation Monitor for the Web and the Foundation for a New Ecosystem.
Proceedings of the RoboCup 2022:, 2022


An Embedded Monocular Vision Approach for Ground-Aware Objects Detection and Position Estimation.
Proceedings of the RoboCup 2022:, 2022

Towards an Autonomous RoboCup Small Size League Robot.
Proceedings of the Latin American Robotics Symposium, 2022

2021
Supporting Detection of Near and Far Pedestrians in a Collision Prediction System.
Proceedings of the 16th International Joint Conference on Computer Vision, 2021

rSoccer: A Framework for Studying Reinforcement Learning in Small and Very Small Size Robot Soccer.
Proceedings of the RoboCup 2021: Robot World Cup XXIV, 2021

Dataset and Benchmarking of Real-Time Embedded Object Detection for RoboCup SSL.
Proceedings of the RoboCup 2021: Robot World Cup XXIV, 2021

Optimized Wireless Control and Telemetry Network for Mobile Soccer Robots.
Proceedings of the RoboCup 2021: Robot World Cup XXIV, 2021

A Telemetry-Based PI Tuning Strategy for Low-Level Control of an Omnidirectional Mobile Robot.
Proceedings of the RoboCup 2021: Robot World Cup XXIV, 2021

Occupancy Grid Map Estimation Based on Visual SLAM and Ground Segmentation.
Proceedings of the Latin American Robotics Symposium, 2021

Mechanical and Dynamic Analysis for Design and Development of a RoboCup SSL Dribbling Mechanism<sup>*</sup>.
Proceedings of the Latin American Robotics Symposium, 2021

Supervised Training of a Simple Digital Assistant for a Free Crop Clinic.
Proceedings of the Intelligent Systems - 10th Brazilian Conference, 2021

2020
An FPGA-based real-time occlusion robust stereo vision system using semi-global matching.
J. Real Time Image Process., 2020

An embedded automatic license plate recognition system using deep learning.
Des. Autom. Embed. Syst., 2020

An Efficient Method for Porosity Properties Extraction of Carbonate Rocks.
Proceedings of the 33rd SIBGRAPI Conference on Graphics, Patterns and Images, 2020

A Strategy to Support Streaming Communication using the Intel HARPv2 Platform: A Case Study in Stereo Vision Application.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A Data Analysis Graphical user Interface for RoboCup 2D Soccer Simulation League.
Proceedings of the Latin American Robotics Symposium, 2020

An Analysis of Reinforcement Learning Applied to Coach Task in IEEE Very Small Size Soccer.
Proceedings of the Latin American Robotics Symposium, 2020

2019
An ensemble strategy for Haplotype Inference based on the internal variability of algorithms.
Proceedings of the International Joint Conference on Neural Networks, 2019

Latin hypercube initialization strategy for design space exploration of deep neural network architectures.
Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2019

Towards better generalization in WLAN positioning systems with genetic algorithms and neural networks.
Proceedings of the Genetic and Evolutionary Computation Conference, 2019

2018
Towards a greater reliability of driver/device communication around the system life cycle through a contract-based protocol specification.
IET Cyper-Phys. Syst.: Theory & Appl., 2018

An FPGA-based Hardware Accelerator for Scene Text Character Recognition.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

An Embedded Automatic License Plate Recognition System Using Deep Learning.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

An FPGA-Based RFID Baseband Processor Using a RISC-V Platform.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
Hardware module for low-resource and real-time stereo vision engine using semi-global matching approach.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
An efficient static gesture recognizer embedded system based on ELM pattern recognition algorithm.
J. Syst. Archit., 2016

A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement.
Proceedings of the VI Brazilian Symposium on Computing Systems Engineering, 2016

A hardware accelerator for the alignment of multiple DNA sequences.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

An FPGA-based accelerator for multiple real-time template matching.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Extreme Value Theory for Estimating Task Execution Time Bounds: A Careful Look.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

A MPSoC cache design space exploration approach based on ABC algorithm to optimize energy consumption and performance.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Oolong: A Baseband processor extension to the RISC-V ISA.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

A hardware accelerator for the alignment of multiple DNA sequences in forensic identification.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Temporized data prefetching algorithm for NoC-based multiprocessor systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
A high performance hardware accelerator for dynamic texture segmentation.
J. Syst. Archit., 2015

Extreme Learning Machine for Real Time Recognition of Brazilian Sign Language.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

2014
The Design of an Image Converting and Thresholding Hardware Accelerator.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

Balanced Prefetching Aggressiveness Controller for NoC-based Multiprocessor.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

An approach for multi-task and multi-application mapping onto NoC-based MPSoC.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Towards more reliable embedded systems through a mechanism for monitoring driver devices communication.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
An Ant Colony metaheuristic for energy aware application mapping on NoCs.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Brazilian symposium on computing system engineering.
ACM SIGOPS Oper. Syst. Rev., 2012

An Optimization Mechanism Intended for Static Power Reduction Using Dual-VthTechnique.
J. Electr. Comput. Eng., 2012

Communication software synthesis from UML-ESL models.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011
Label-Free Electrochemical Detection of the Specific Oligonucleotide Sequence of Dengue Virus Type 1 on Pencil Graphite Electrodes.
Sensors, 2011

An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms.
Int. J. Reconfigurable Comput., 2011

Device Driver Generation and Checking Approach.
Proceedings of the Brazilian Symposium on Computing System Engineering, 2011

HdSC: a fast and preemptive modeling for on host HdS development.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
A high performance full pipelined arquitecture of MLP Neural Networks in FPGA.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A design flow based on a domain specific language to concurrent development of device drivers and device controller simulation models.
Proceedings of the 12th International Workshop on Software and Compilers for Embedded Systems, 2009

A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2008
A table-based method for single-pass cache optimization.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Aquarius: a dynamically reconfigurable computing platform.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A one-shot configurable-cache tuner for improved energy and performance.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A computational reflection mechanism to support platform debugging in SystemC.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

Configurable cache subsetting for fast cache tuning.
Proceedings of the 43rd Design Automation Conference, 2006

2005
The ArchC Architecture Description Language and Tools.
Int. J. Parallel Program., 2005

Platform designer: An approach for modeling multiprocessor platforms based on SystemC.
Des. Autom. Embed. Syst., 2005

A SystemC-only design methodology and the CINE-IP multimedia platform.
Des. Autom. Embed. Syst., 2005

ipPROCESS: Using a Process to Teach IP-Core Development.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

IpPROCESS: a Development Process for Soft IP-Cord.
Proceedings of the Forum on specification and Design Languages, 2005

Processor Centric Specification and Modelling of MPSoCs.
Proceedings of the Forum on specification and Design Languages, 2005

Vital Signs Remote Management System for PDAs.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
A Constructive Approach to Hardware/Software Partitioning.
Formal Methods Syst. Des., 2004

A Petri net based method for functional and interconnect units estimation.
Proceedings of the IEEE International Conference on Systems, 2004

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology.
Proceedings of the 2004 Design, 2004

2003
Exploring Memory Hierarchy with ArchC.
Proceedings of the 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2003), 2003

2002
On the Importance, Problems and Solutions of Pointer Synthesis.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Interface Generation for Concurrent Processes During Hardware/Software Co-synthesis.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

2001
A Petri Net Based Approach for Hardware/Software Partitioning.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

A Petri Net Based Method for Resource Estimation: An Approach Considering Data-Dependency, Casual and Temporal Precedences.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design.
Proceedings of the SOC Design Methodologies, 2001

2000
Resource sharing estimation by Petri nets in PISH hardware/software co-design system.
Proceedings of the IEEE International Conference on Systems, 2000

Using Petri nets for data dependency analysis.
Proceedings of the IEEE International Conference on Systems, 2000

Methods Based on Petri Net for Resource Sharing Estimation.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999
A Petri Net Model for Hardware/Software Codesign.
Des. Autom. Embed. Syst., 1999

1998
A safe, accurate intravenous infusion control system.
IEEE Micro, 1998

A Petri net based approach for performing the initial allocation in hardware/software codesign.
Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

An Algebraic Approach to Combining Processes in a Hardware/Software Partitioning Environment.
Proceedings of the Algebraic Methodology and Software Technology, 1998

1997
Computing communication cost by Petri nets for hardware/software codesign.
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997

A Normal Form Reduction Strategy for Hardware/Software Partitioning.
Proceedings of the FME '97: Industrial Applications and Strengthened Foundations of Formal Methods, 1997

A FPGA-based Implementation of an Intravenous Infusion Controller System.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Capturing Time Constraints by Using Petri-nets in the Context of Hardware/Software Codesign.
Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping (RSP '96), 1996

1994
A method for partitioning UNITY language in hardware and software.
Proceedings of the Proceedings EURO-DAC'94, 1994

Towards provably correct hardware/software partitioning using occam.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Hardware/software partitioning using UNITY.
PhD thesis, 1993


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