Edgar Rieger

According to our database¹, Edgar Rieger authored at least 8 papers between 2004 and 2005.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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2005

Extended abstract: an environment for design verification of smart card systems using attack simulation in SystemC.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

Power consumption profile analysis for security attack simulation in smart cards at high abstraction level.

[BibT_eX]

[DOI]

Proceedings of the EMSOFT 2005, 2005

Methodologies for Designing Power-Aware Smart Card Systems.

[BibT_eX]

[DOI]

Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

An Abstraction and Optimization Approach using HW/SW Co-design Techniques to get Power Aware Smart Card Solutions.

[BibT_eX]

Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

2004

A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

SystemC Based Design Space Exploration for Power Aware Smart Cards.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2004

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

High Level Fault Injection for Attack Simulation in Smart Cards.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Edgar Rieger

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