Edgar-Andrei Vega-Ochoa

According to our database1, Edgar-Andrei Vega-Ochoa authored at least 6 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2020
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.
IEEE Trans. Emerg. Top. Comput., 2020

2019
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Direct optimization of a PCI express link equalization in industrial post-silicon validation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Jitter tolerance acceleration using the golden section optimization technique.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2014
SMV methodology enhancements for high speed I/O links of SoCs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014


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