Echere Iroaga
According to our database1,
Echere Iroaga
authored at least 4 papers
between 2005 and 2018.
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Bibliography
2018
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2007
IEEE J. Solid State Circuits, 2007
2005
A background correction technique for timing errors in time-interleaved analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005