E. Scott Fehr

According to our database, E. Scott Fehr authored at least 4 papers between 1979 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

An Integrated Hardware Array for Very High Speed Logic Simulation.

E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott

VLSI Design, 1996

1995

Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.

Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1981

A VLSI Architecture for Software Structure: The Intel 8086.

Alfred C. Hartmann, E. Scott Fehr

IEEE Micro, 1981

1979

Design Considerations for the VLSI Processor of X-tree.

David A. Patterson, E. Scott Fehr, Carlo H. Séquin

Proceedings of the 6th Annual Symposium on Computer Architecture, 1979