E. R. Hsieh

According to our database, E. R. Hsieh authored at least 6 papers between 1977 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

3-bits-per-cell 2T32CFE nvTCAM by Angstrom-laminated Ferroelectric Layers with 10¹¹ Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching.

E. R. Hsieh, Ying-Tsan Tang, Cheng-Rui Liu, Sheng-Min Wang, Y. L. Hsueh, R. Q. Lin, Y. X. Huang, Yu-Ting Chen

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 10¹⁰ Cycles of Endurance, and Decade Lifetime at 103 °C.

E. R. Hsieh, J. K. Chang, T. Y. Tang, Y. J. Li, C. W. Liang, M. Y. Lin, S. Y. Huang, C. J. Su, J. C. Guo, Steve S. Chung

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path.

W. Y. Yang, E. R. Hsieh, C. H. Cheng, B. Y. Chen, K. S. Li, Steve S. Chung

Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020

A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory.

E. R. Hsieh, H. W. Cheng, Z. H. Huang, C. H. Chuang, S. P. Yang, Steve S. Chung

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond.

E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

1977

Delay test generation.

E. R. Hsieh, Robert A. Rasmussen, L. J. Vidunas, W. T. Davis

Proceedings of the 14th Design Automation Conference, 1977