E. M. Bazizi

According to our database1, E. M. Bazizi authored at least 13 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024

Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling.
Proceedings of the IEEE International Memory Workshop, 2024

D2W Hybrid Bonding Challenges for HBM.
Proceedings of the IEEE International Memory Workshop, 2024

2023
BEOL Interconnect Innovation: Materials, Process and Systems Co-optimization for 3nm Node and Beyond.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Contact Cavity Shaping and Selective SiGe: B Low-Temperature Epitaxy Process Solution for sub 10<sup>-9</sup> Ω.cm<sup>2</sup> Contact Resistivity in Nonplanar FETs.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
Integration scheme for 3D NAND with nonreplacement word line and its cell characteristics investigation.
Proceedings of the IEEE International Memory Workshop, 2021

2020
Modeling and Optimization of Advanced 3D NAND Memory.
Proceedings of the 2020 Device Research Conference, 2020

2019
TCAD Simulation on FinFET n-type Power Device HCI Reliability Improvement.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Low-Frequency Noise Reduction in 22FDX®: Impact of Device Geometry and Back Bias.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Highly-Doped Through-Contact Silicon Epi Design at 3 nm node.
Proceedings of the Device Research Conference, 2019

2014
Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation.
Proceedings of the 44th European Solid State Device Research Conference, 2014


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