Dylan C. Stow

Orcid: 0000-0003-4302-5649

According to our database1, Dylan C. Stow authored at least 13 papers between 2012 and 2019.

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Bibliography

2019
Network-on-Chip Design Guidelines for Monolithic 3-D Integration.
IEEE Micro, 2019

Power Profiling of Modern Die-Stacked Memory.
IEEE Comput. Archit. Lett., 2019

Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Die Stacking Is Happening.
IEEE Micro, 2018

Cost-efficient 3D Integration to Hinder Reverse Engineering During and After Manufacturing.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Cost-effective design of scalable high-performance systems using active and passive interposers.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Security Threats and Countermeasures in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Thermal-aware 3D design for side-channel information leakage.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2012
Yield-driven minimum energy CMOS cell design.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012


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