Duy-Hieu Bui

According to our database, Duy-Hieu Bui authored at least 15 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages.

Duy-Hieu Bui, Duc-Manh Tran, Daniele D. Caviglia, Orazio Aiello

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Hardware Architecture of NIST Lightweight Cryptography Applied in IPSec to Secure High-Throughput Low-Latency IoT Networks.

Sy-Nam Tran, Van-Thuc Hoang, Duy-Hieu Bui

IEEE Access, 2023

Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags.

Hiep Manh Dao, Vincent Beroulle, Yann Kieffer, Xuan-Tu Tran, Duy-Hieu Bui

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022

An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection.

Ngo-Doanh Nguyen, Duy-Hieu Bui, Fawnizu Azmadi Hussin, Xuan-Tu Tran

Proceedings of the International Conference on IC Design and Technology, 2022

2020

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks.

Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Hung K. Nguyen, Cong-Kha Pham

EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020

A Lightweight AEAD encryption core to secure IoT applications.

Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran

Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks.

Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization.

Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2017

AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.

Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran

IEEE Trans. Very Large Scale Integr. Syst., 2017

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems.

Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné

J. Low Power Electron., 2017

AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures.

Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.

Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran

Proceedings of the International Conference on IC Design and Technology, 2016

2014

Reducing temporal redundancy in MJPEG using Zipfian estimation techniques.

Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

H.264/AVC hardware encoders and low-power features.

Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

High-performance adaption of ARM processors into Network-on-Chip architectures.

Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013