Dusan Bozilov

Orcid: 0000-0001-8629-4115

According to our database1, Dusan Bozilov authored at least 8 papers between 2017 and 2022.

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Bibliography

2022
Optimized threshold implementations: securing cryptographic accelerators for low-energy and low-latency applications.
J. Cryptogr. Eng., 2022

2021
New First-Order Secure AES Performance Records.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

2020
PRINCEv2 - More Security for (Almost) No Overhead.
IACR Cryptol. ePrint Arch., 2020

On Optimality of d + 1 TI Shared Functions of 8 Bits or Less.
IACR Cryptol. ePrint Arch., 2020

2019
Design Trade-offs in Threshold Implementations.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Optimized Threshold Implementations: Minimizing the Latency of Secure Cryptographic Accelerators.
Proceedings of the Smart Card Research and Advanced Applications, 2019

2018
Teaching HW/SW codesign with a Zynq ARM/FPGA SoC.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

2017
A Note on 5-bit Quadratic Permutations' Classification.
IACR Trans. Symmetric Cryptol., 2017


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