Dursun Baran

Microelectron. J., November, 2023

Exploration of Simplified Adaptation Functions for Adaptive Pre-Distortion Implementations.

[BibT_eX]

[DOI]

Proceedings of the 31st Signal Processing and Communications Applications Conference, 2023

2022

A time-interleaved ADC calibration technique for spectrum monitoring applications.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A Digital Filter Design at Auxiliary Receiver for Optimal Pre-Distortion Performance.

[BibT_eX]

[DOI]

Proceedings of the 30th Signal Processing and Communications Applications Conference, 2022

2021

An Approximate Timing-Mismatch Calibration Technique for Interleaved ADCs.

[BibT_eX]

[DOI]

Enes Karav

Hakan Yaren

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2015

Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015

2011

A Quick Method for Energy Optimized Gate Sizing of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Multiplier structures for low power applications in deep-CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Energy-Efficient Design Methodologies: High-Performance VLSI Adders.

[BibT_eX]

[DOI]

Bart R. Zeydel

IEEE J. Solid State Circuits, 2010

Energy efficient implementation of parallel CMOS multipliers with improved compressors.

[BibT_eX]

[DOI]