Dumitru Potop-Butucaru

Orcid: 0000-0003-3672-6156

Affiliations:
  • INRIA, France


According to our database1, Dumitru Potop-Butucaru authored at least 27 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Bidirectional Reactive Programming for Machine Learning.
CoRR, 2023

Semantics foundations of PsyC based on synchronous Logical Execution Time.
Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023

2022
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers.
ACM Trans. Archit. Code Optim., 2022

2019
Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware.
ACM Trans. Archit. Code Optim., 2019

Sheep in wolf's Clothing: Implementation Models for Dataflow Multi-Threaded Software.
Proceedings of the 19th International Conference on Application of Concurrency to System Design, 2019

2018
Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators.
Proceedings of the 18th International Conference on Application of Concurrency to System Design, 2018

2015
From Dataflow Specification to Multiprocessor Partitioned Time-triggered Real-time Implementation.
Leibniz Trans. Embed. Syst., 2015

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2015

Real-Time Systems Compilation. (Compilation de systèmes temps réel).
, 2015

2014
Predicate-aware, makespan-preserving software pipelining of scheduling tables.
ACM Trans. Archit. Code Optim., 2014

Reconciling performance and predictability on a many-core through off-line mapping.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
Integrated Worst-Case Execution Time Estimation of Multicore Applications.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013

2012
Programmable routers for efficient mapping of applications onto NoC-based MPSoCs.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations.
Fundam. Informaticae, 2011

2010
Semantics-preserving implementation of synchronous specifications over dynamic TDMA distributed architectures.
Proceedings of the 10th International conference on Embedded software, 2010

From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations.
Proceedings of the Synthesis of Embedded Software, 2010

2009
Clock-driven distributed real-time implementation of endochronous synchronous programs.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

Synchronous Hypothesis and Polychronous Languages.
Proceedings of the Embedded Systems Design and Verification, 2009

2007
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications.
Fundam. Informaticae, 2007

Necessary and sufficient conditions for deterministic desynchronization.
Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

Compiling Esterel.
Springer, ISBN: 978-0-387-70626-9, 2007

2006
Concurrency in Synchronous Systems.
Formal Methods Syst. Des., 2006

2005
The Synchronous Hypothesis and Synchronous Languages.
Proceedings of the Embedded Systems Handbook., 2005

Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits.
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

From multi-clocked synchronous processes to latency-insensitive modules.
Proceedings of the EMSOFT 2005, 2005

2003
Optimizations for Faster Execution of Esterel Programs.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003


  Loading...