Duckhwan Kim

Orcid: 0000-0002-6494-2182

Affiliations:
  • Georgia Institute of Technology, Atlanta, GA, USA


According to our database1, Duckhwan Kim authored at least 19 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2019
Neurocube: Energy-Efficient Programmable Digital Deep Learning Accelerator based on Processor in Memory Platform.
PhD thesis, 2019

Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Heterogeneous integration for artificial intelligence: Challenges and opportunities.
IBM J. Res. Dev., 2019

2018
Adaptive Precision Cellular Nonlinear Network.
IEEE Trans. Very Large Scale Integr. Syst., 2018

DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
A Power-Aware Digital Multilayer Perceptron Accelerator with On-Chip Training Based on Approximate Computing.
IEEE Trans. Emerg. Top. Comput., 2017

NeuroTrainer: An Intelligent Memory Module for Deep Learning Training.
CoRR, 2017

Energy-efficient neural image processing for Internet-of-Things edge devices.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A Programmable Hardware Accelerator for Simulating Dynamical Systems.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Adaptive weight compression for memory-efficient neural networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Pulsed-latch ASIC synthesis in industrial design flow.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2009
Animal-Robot Interaction for pet caring.
Proceedings of the IEEE International Symposium on Computational Intelligence in Robotics and Automation, 2009


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