Duckgyu Shin

According to our database, Duckgyu Shin authored at least 12 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems.

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Access, 2024

2023

Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing.

Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Neural Networks Learn. Syst., December, 2023

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing.

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing.

Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

CoRR, 2023

Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems.

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

CoRR, 2023

Improving Stochastic Quantum-Like Annealing Based on Rerandomization.

Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Stochastic Implementation of Simulated Quantum Annealing on PYNQ.

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN.

Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

FLAP, 2022

Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing.

Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2020

Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.

Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu

FLAP, 2020

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Access, 2020

2019

FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.

Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019